Sample-and-Hold Circuit__論文

kevinwjs

Low Power, High Performance Sample-and-Hold Circuit__論文

This master thesis describes the design of a track-and-hold (T&H) circuit
with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a
0.18μm CMOS process with a supply voltage of 1.8 Volt. The circuit is
supposed to work together with a 10bit pipelined analog to digital converter.
A switched capacitor topology is used for the T&H circuit and the amplifier
is a folded cascode OTA with regulated cascode. The switches used are of
transmission gate type.
The thesis presents the design decisions, design phase and the theory needed
to understand the design decisions and the considerations in the design
phase.
The results are based on circuit level SPICE simulations in Cadence with
foundry provided BSIM3 transistor models. They show that the circuit has
10bit resolution and 7.6mW power consumption, for the worst-case
frequency of 30MHz. The requirements of the dynamic performance are all
fulfilled, most of them with large margins

soupdawn

xiexeifenxaing

winsymbol

好资料，下来看看！！

jjw3310

Where!!!!!!!!!!!!!

kevinwjs

http://www.eetop.com.cn/bbs/thread-100294-1-1.html

limingchou

s8553warrior

thanks for sharing

sunflower

thank you

NCTUGICE

感謝分享囉
應該寫的很不錯