免费：Hardware design Guideline with Verilog-RTL

xudeqiang

As design circuit size gets larger, efficient reuse of design property has become extremely important.
The design property, which is also called IP (Intellectual Property), is essential technology to
realize System-on-a-Chip.
The organization called VSI (Virtual Socket Interface) is now trying to commonize IP to enable us
to structure a system by purchasing IP from multiple vendors that a large-scale system can easily
be integrated into a single chip. Therefore, a circuit, which is larger than conventional ones, can
be designed within the similar timeframe.
Software IP is described in RTL (Register Transfer Level) by using mainly HDL (Hardware Description
Language).
By having IP described in RTL, changes can easily be made to the HDL description. Also, in the
parameterized descriptions, a circuit can easily be changed according to the object of an application.
These software IP are realized in gate level circuits at the end by using logic synthesis tools and by
specifying design constraints and technology.
The design constraint includes specification of timing condition, area, and operation environment
etc. as the required circuit performance. If the constraint given at the time of synthesis is not
appropriate, the circuit may be synthesized incorrectly and therefore it becomes unlikely to meet
the target performance. If description is not appropriate, it will also become hard to meet the
target performance.

[ 本帖最后由 xudeqiang 于 2008-3-13 19:02 编辑 ]

weixbox

thank Xu

Allen09

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Allen09

222  xia

unclebearbear

very very good

unclebearbear

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csjtek

waiting for so long , Now , it is free ,
Thanks a lots

csjtek

Thanks very much.

jcchan

很好的資料，感謝大大無私的分享。

eng4wo

thanks