VHDL 语言 编写38 译码器（新手）

selber

我们被要求分别用 behavioral 和 structureal model 编写 38译码器 还要 写 testbench program
请大家帮助修改下我写的两个model的程序，并请教下testbench program如何编写：）
behavioral model
ibrary ieee;         
use ieee.std_logic_1164.all;  
entity 38decoder is      
   Port(D0:in std_logic_vector(2 down to 0);clk,en:in bit;  
          Q0ut std_logic_vector(7 down to 0));
end entity 38decoder;
architechture behav of 38decoder is  
begin
wait until clk='1'  
process(D0,en)      
begin
if (en='0') then Q0<="zzzzzzzz" after 2ns;
else
case D0 is                                 
when "000" => Q0<= "00000001" after 2ns;   
when "001" => Q0<= "00000010" after 2ns;
when "010" => Q0<= "00000100" after 2ns;
when "011" => Q0<= "00001000" after 2ns;
when "100" => Q0<= "00010000" after 2ns;
when "101" => Q0<= "00100000" after 2ns;
when "110" => Q0<= "01000000" after 2ns;
when "111" => Q0<= "10000000" after 2ns;   
when others=> Q0<= "zzzzzzzz" after 2ns;
end case;
end if;
end process;
end architechture behav;

structureal model

entity 38decoder is
Port(D0,D1,D2,clk,en:in bit;  
          Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7ut bit);
end entity 38decoder;
architecture struct of 38decoder is
component declaration         
signal int_clk : bit;         
begin                              
  bit:
    port map(int_clk,Q0);           
  bit1:
    port map(D0,int_clk,Q1);        
  bit2:
    port map(D1,int_clk,Q2);      
  bit3:
    port map(D1,D0,int_clk,Q3);     
  bit4:
    port map(D2,int_clk,Q4);        
  bit5:
    port map(D2,D0,int_clk,Q5);     
  bit6:
    port map(D2,D1,int_clk,Q6);     
  bit7:
    port map(D2,D1,D0,int_clk,Q7);  
  gate: and2
    port map (en, clk, int_clk);   
end architecture struct;

kaiwa

学习学习

qhb9522

到处都是啊

Wangbin_1984

testbench 可以借助Quartus II 软件自己生成啊！

wbh9527

还没试过，怎么生成啊