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本帖最后由 hardmany 于 2017-6-4 11:21 编辑
麻烦帮忙下篇论文:A 5.4GS/s 12b 500mW pipeline ADC in 28nm CMOSAbstract:A 5.4GS/s 12b 2-way interleaved pipeline ADC is presented. To achieve high speed, a complementary switched-capacitor amplifier is proposed, along with ping-pong amplifier sharing and digital MDAC equalization. The ADC achieves 61dB SNR and 57dB THD up to 2.6GHz input frequency at 5.4GS/s, consumes 500mW and occupies 0.4mm2 area in 28nm CMOS.
Published in: VLSI Circuits (VLSIC), 2013 Symposium on
Date of Conference: 12-14 June 2013
Date Added to IEEE Xplore: 16 August 2013
ISBN Information:
INSPEC Accession Number: 13711772
Publisher: IEEE
Conference Location: Kyoto, Japan
谢谢。
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