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50资产
按网上查的方法来,在最后烧bit文件时总是报下面的warning:
- WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
- INFO: [Labtools 27-1434] Device xc7k410t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
- WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. You must manually launch hw_server
- with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4.
- To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
- WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7k410t_0 and the probes file D:/Vivado/xc7k410t-2ffg900/ddr_slave_410t_20150527_1/ddr_slave_410t_20150527_1.runs/impl_1/debug_nets.ltx.
- The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 1 ILA core(s) and 0 VIO core(s).
- Resolution:
- 1. Reprogram device with the correct programming file and associated probes file OR
- 2. Goto device properties and associate the correct probes file with the programming file already programmed in the device.
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大概是说设计里没有ILA core,但是debug文件里有ILA core,而且debug probes窗口下什么也没有。但是,我综合后明明插入了debug core呀,而且在约束文件里也自动生成了相关信息,查看schematic,也添加了debug相关的两个元件,为毛program时就是看不到呢?
不知道有没有人遇到过类似的情况,求指点,万分感谢! |
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