warning，提示can‘t read link library

momoi11 · 发表于 2015-5-5 11:50:17

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才开始用DC，我自己写的.v文件和dc.setup以及tcl都在一个叫fsm_moore的文件夹里，dc_setup是照着别人写的，库文件在另一个叫library文件夹里，我感觉路径没有错。
（1）启动DC后，一直提示Warning: Can't read link_library file 'your_library.db'. (UID-3)。我用别人的例子试过也是一样，不知道问题在哪里。
（2）还有就是，这个your_library.db指我设置的库，还是一个其他的东西？
希望有热心人解释一下，非常感谢！

终端信息：
Loading db file '/eda/synopsys/syn/2012.06/libraries/syn/gtech.db'
Loading db file '/eda/synopsys/syn/2012.06/libraries/syn/standard.sldb'
Loading link library 'gtech'
Loading verilog file '/home/klin/Desktop/qixin_lab/qixin_verilog_CODE/fsm_moore/fsm_moore.v'
Detecting input file type automatically (-rtl or -netlist).
Running DC verilog reader
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Warning: Can't read link_library file 'your_library.db'. (UID-3)
Compiling source file /home/klin/Desktop/qixin_lab/qixin_verilog_CODE/fsm_moore/fsm_moore.v

dc.setup文件：
#######################################################
#
# dc_shell TcL startup script:
#
set designer "klin"
set company "QiXin"
#
# Some design environment variables:
#
set search_path "$search_path ../library"
#
# tc = Typical; bc = Best; wc = Worst:
set target_library typical.db
set link_library "* $target_library"
#
set symbol_library tsmc090.sdb
#
# ---------------------------------
#
# Set up a work library for this design in a subdirectory:
define_design_lib fsm_moore -path ./fsm_mooreSynth