Constraining Designs for Synthesis and Timing Analysis

heyitsyou · 发表于 2014-12-4 15:32:41

非常感谢

suchthat · 发表于 2014-12-5 14:19:43

回复 113# heyitsyou

非常感謝

jiee · 发表于 2015-1-5 23:01:03

eetopjpang · 发表于 2015-4-5 06:41:37

good !

eetopjpang · 发表于 2015-4-6 02:28:52

very good!

kharthik · 发表于 2015-4-8 19:43:01

回复 1# bingjunpeng

Nice update.
Can I get the model .sdc file and steps to generate .sdc in synopsys DC.

I am struck up with this issue for long.

Please help me.

tide · 发表于 2015-4-9 16:48:02

eetop

chensongtao9 · 发表于 2015-4-9 21:58:48

谢谢楼主的分享

yahuamvp · 发表于 2015-7-16 20:10:55

超级感谢，正好在做DC和STA相关

johnli330 · 发表于 2015-7-17 10:03:33

写得非常好

[资料] Constraining Designs for Synthesis and Timing Analysis

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