【重磅推出】step-by-step functional verification with systemverilog and ovm

redleaf1988 · 发表于 2014-12-2 20:25:55

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

您需要登录才可以下载或查看，没有账号？注册

x

Step-by-step Functional Verification with SystemVerilog and OVM 41-fYsCgqbL._BO2,204,203,200_PIsitb-sticker-arrow-click,TopRight,35,-76_AA300_SH20_OU01_.jpg

41-fYsCgqbL._BO2,204,203,200_PIsitb-sticker-arrow-click,TopRight,35,-76_AA300_SH20_OU01_.jpg

看到大家都在找这本书，在这里和大家分享一下，希望有所帮助。

以下是这本经典好书的评论：(摘自Amazon)
"This detailed, step-by-step guide provides a thorough introduction to SystemVerilog and the Open Verification Methodology (OVM). With many examples and clear descriptions, it should be helpful to anyone involved in IC functional verification."
Richard Goering, Editor-in-Chief , SCDsource

"Dr. Iman brings together all the essential elements to understand the use and application of OVM. Those with limited SystemVerilog knowledge will find Step-by-Step Functional Verification with SystemVerilog and OVM offers a complete introduction to SystemVerilog, and the SystemVerilog-savvy will find this a comprehensive OVM reference. This book has everything design and verification engineers would want to know to apply OVM to their most pressing challenges."
Dennis Brophy , Director of Strategic Business Development , Mentor Graphics

"The author of this book is well known in the design community as a leader in the verification space. SystemVerilog has provided a major step in our capability to verify our designs, especially in today’s world of 40 million gate SoCs. The combination has produced a very thorough step by step guide to the latest in verification methodology."
Gary Smith, Chief Analyst, Gary Smith EDA

"The Open Verification Methodology (OVM) is one of the most quickly and widely adopted new solutions ever for verifying complex chips. This book walks the reader through the OVM as well as the SystemVerilog language constructs upon which it is built. The breadth of Step-by-Step Functional Verification with SystemVerilog and OVM and its pragmatic approach make it an invaluable resource for both novice and experienced verification engineers."
Ted Vucurevich, CTO, Cadence

step-by-step functional verification with systemverilog and ovm.part1.rar (4 MB, 下载次数: 351 )

step-by-step functional verification with systemverilog and ovm.part2.rar (4 MB, 下载次数: 316 )

step-by-step functional verification with systemverilog and ovm.part3.rar (4 MB, 下载次数: 355 )

step-by-step functional verification with systemverilog and ovm.part4.rar (4 MB, 下载次数: 353 )

step-by-step functional verification with systemverilog and ovm.part5.rar (4 MB, 下载次数: 238 )

step-by-step functional verification with systemverilog and ovm.part6.rar (4 MB, 下载次数: 326 )

step-by-step functional verification with systemverilog and ovm.part7.rar (2 MB, 下载次数: 239 )