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发表于 2014-4-4 14:09:41
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本帖最后由 mqlitong 于 2014-4-5 20:51 编辑
写个小程序,仅供参考一下
补充说明一下,仿真时clk为50MHz信号
- module counter(
- clk,
- signal,
- rst_n,
- o_signal//for test
- );
-
- input clk;
- input signal;
- input rst_n;
- //for test
- output o_signal;
- assign o_signal = signal;
- reg signal_reg;
- wire signal_wire;
- assign signal_wire = signal_reg;
- reg[7:0] count;
- reg[31:0] cnt_1;
- reg[31:0] cnt_2;
- always@(posedge clk or negedge rst_n)
- begin
- if (!rst_n)
- begin
- count <= 8'd0;
- cnt_1 <= 32'd0;
- cnt_2 <= 32'd0;
- end
- end
- always@(posedge clk)
- signal_reg <= signal;
- always@(posedge clk)
- begin
- if (signal_reg == 1)
- count <= count + 1'b1;
- else
- count <= 8'b0;
- end
- always@(negedge signal_wire)
- begin
- if ((count == 8'd50) && (!signal_wire))
- cnt_1 <= cnt_1 + 1'b1;
- else if ((count == 8'd25) && (!signal_wire))
- cnt_2 <= cnt_2 +1'b1;
- else ;
- end
- endmodule
复制代码
有仿真如下:
ISE软件仿真
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