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楼主 |
发表于 2012-12-4 11:02:22
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贴出来我写的代码:
module div5 (
clk_100m,
rst_b ,
clk_20m
);
input clk_100m ;
input rst_b ;
output clk_20m ;
wire clk_100m ;
wire rst_b ;
wire clk_20m ;
wire clk_100m_p ; //100m inverter
reg [2:0] cnt_20m_n ;//generate by positive 100m ,counter
reg [2:0] cnt_20m_p ;//generate by negative 100m ,counter
reg clk_20m_n ;
reg clk_20m_p ;
assign clk_100m_p = ~clk_100m ;
always@ (posedge clk_100m or negedge rst_b)
if (!rst_b)
cnt_20m_n <= 3'b000 ;
else if (cnt_20m_n ==3'b100)
cnt_20m_n <= 3'b000 ;
else
cnt_20m_n <= cnt_20m_n +1 ;
always@ (negedge clk_100m_p or negedge rst_b)
if (!rst_b)
cnt_20m_p <= 3'b000 ;
else if (cnt_20m_p ==3'b100)
cnt_20m_p <= 3'b000 ;
else
cnt_20m_p <= cnt_20m_p +1 ;
always@ (posedge clk_100m or negedge rst_b)
if (!rst_b)
clk_20m_n <= 1'b0 ;
else if (cnt_20m_n ==3'b010)
clk_20m_n <= 1'b1 ;
else if (cnt_20m_n ==3'b100)
clk_20m_n <= 1'b0 ;
always@ (negedge clk_100m or negedge rst_b)
if (!rst_b)
clk_20m_p <= 1'b0 ;
else if (cnt_20m_p ==3'b010)
clk_20m_p <= 1'b1 ;
else if (cnt_20m_p ==3'b100)
clk_20m_p <= 1'b0 ;
assign clk_20m = clk_20m_n & clk_20m_p ;
endmodule
以下是testbe nch
module test_div5 ;
reg clk_100m ;
reg rst_b ;
wire clk_20m ;
wire clk_100m_ct ;
wire rst_b_ct ;
initial
clk_100m = 1'b0 ;
always clk_100m = ~ clk_100m ;
initial
begin
rst_b = 1'b0 ;
#20 rst_b = 1'b1 ;
end
assign clk_100m_ct = clk_100m ;
assign rst_b_ct = rst_b ;
div5 div5_1 (
.clk_100m (clk_100m_ct),
.rst_b (rst_b_ct) ,
.clk_20m (clk_20m)
);
endmodule |
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