In building the timing constraints, do you need to constrain all IO ports? Can a single port have multi-clocked? How do you set delays for such ports? Can a clock port have multi-clock definition? How do you create clock for this port?
写时序约束时,是否需要对所有的IO端口加约束?一个信号端口是否可以被多个时钟约束?应该如何对这种端口设置delay?一个时钟端口是否可以定义多个时钟?应该如何定义这些时钟?