用VerilogA建模PLL的资料

woodkey · 发表于 2011-6-10 14:53:51

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本帖最后由 helianalog 于 2011-8-1 10:03 编辑

//A Top-Down Verilog-A Design on the Digital Phase-Locked Loop

RT，教你用VerilogA语言搭建PLL的行为级模型！

woodkey · 发表于 2011-6-10 14:54:50

先自己帮自己顶一下，抢占沙发

ana192712 · 发表于 2011-6-10 16:32:10

回复 1# woodkey

woodkey · 发表于 2011-6-10 16:45:00

什么状况，无缘无故被召唤过来

yuqiumax · 发表于 2011-6-11 15:09:28

回复 1# woodkey
麻烦发帖时，说详细点，免得重复下载。

A Top-Down Verilog-A Design on the Digital Phase-Locked Loop
Report of the Project Assignment
Presented for Ph.D Qualifying Exam
By
Ching-Hong Wang
Advisory Committee:
Steven Bibyk, Professor of the ECE Department, Advisor
Bradley D. Clymer, Professor of the ECE Department
Eylem Ekici, Professor of the ECE Department