MIPS 32 bit processor (5 stage pipeline) verilog code

eagleice · 发表于 2011-4-27 02:04:12

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Hi all

The files are compressed as rar file

description of the code

Register File：32 × 32-bit Registers
Instruction Memory：1KB (256 × 32-bit )
Data Memory：32 Bytes (Memories are modeled in Verilog simply as an array of registers, so we did not care about the memory latency)
Address space: Text segment and data segment both begin at address 0x0000 for convenience, different from the real MIPS machine

eagleice · 发表于 2011-4-27 02:05:51

回复 1# eagleice

yellowfly001 · 发表于 2011-4-27 09:44:07

好东西谢谢楼主分享

qq847941010 · 发表于 2011-4-28 09:31:05

Thans

windfly0 · 发表于 2011-4-28 09:55:14

only 7 file ,each file is 0.4mb
total size of crack is 2.7mb
upload complete ,download it

cihchenlin · 发表于 2011-4-28 10:36:25

楼主，好贴啊

niuniu4 · 发表于 2011-4-28 12:31:54

又小又好的东东，谢谢！

aimar327 · 发表于 2011-4-29 23:11:52

有文档没有

teleixi · 发表于 2011-4-30 21:58:27

学习了谢谢

teleixi · 发表于 2011-4-30 22:01:44

good!!!!!!

[资料] MIPS 32 bit processor (5 stage pipeline) verilog code