例子如下:
always @(posedge clk or negedge rstn)
begin
if(~rstn)
........
else
begin
case(state)
IDLE:
state<=s1;
.........
s1 :
state<=s2;
.......
s2 :
state<=s3;
f<=1;
..........
s3 :
......
state<=s2;
endcase
case(second_state)
ss0: begin
if(f==1'b1)
second_state<=ss1;
else
second_state<=ss0;
end
ss1: begin
.............
second_state<=ss0;
f<=1'b0;
end
endcase
always@(posedge clk or negedge xreset)
if (~xreset)
a <= 1'b0;
else begin
a <= 1'b0; //这种并行的写法类似你说的,在一个always的两个状态机内对同一个信号赋值
if(b==0)begin //一般会编译成 b!=0时a=0,else,b==0时a=1,而不会有冲突。
a<= 1'b1;
end
end
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但是会有与设计思想不符的风险。