请教一个错误：刚接触modelsim不熟悉，实在是弄不了。谢谢赐教。

jiereliyi

编译完，启动仿真后就出现这种错误。
# Reading C:/altera/10.0/modelsim_ase/tcl/vsim/pref.tcl
# do vga_nios_run_msim_rtl_vhdl.do
# if {[file exists rtl_work]} {
#         vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying C:\altera\10.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied C:\altera\10.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
#
# vlog -vlog01compat -work work +incdir+D:/nios_project/vga {D:/nios_project/vga/vga_controller_stream.v}
# Model Technology ModelSim ALTERA vlog 6.5e Compiler 2010.02 Feb 27 2010
# -- Compiling module vga_controller_stream
#
# Top level modules:
#         vga_controller_stream
# vcom -93 -work work {D:/nios_project/vga/VGA_Timing.vhd}
# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity vga_timing
# -- Compiling architecture translated of vga_timing
# vcom -93 -work work {D:/nios_project/vga/vga_pixel_fifo.vhd}
# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity vga_pixel_fifo
# -- Compiling architecture syn of vga_pixel_fifo
#
# vcom -93 -work work {D:/nios_project/vga/simulation/modelsim/vga_testbench.vhd}
# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package numeric_std
# -- Compiling entity vga_testbench
# -- Compiling architecture behavior of vga_testbench
#
# vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L cyclone -L rtl_work -L work -voptargs="+acc" vga_testbench
# vsim -L altera -L lpm -L sgate -L altera_mf -L cyclone -L rtl_work -L work -voptargs=\"+acc\" -t 1ps vga_testbench
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading ieee.numeric_std(body)
# Loading work.vga_testbench(behavior)
# ALTERA version supports only a single HDL
# ** Error: (vsim-3039) D:/nios_project/vga/simulation/modelsim/vga_testbench.vhd(40): Instantiation of 'vga_controller_stream' failed.
#         Region: /vga_testbench
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./vga_nios_run_msim_rtl_vhdl.do PAUSED at line 14

demonsolar

没有源代码，不好定位，你最好找个装有quartus的人帮你试一下。我用的是ISE

venysky

Modelsim已经指出你bench文件vga_testbench.vhd在实例化顶层vga_controller_stream时出现错误(line40)，先检查testbench代码有没有错误吧。

jiereliyi

谢谢。我试试，这个论坛好，人气

jiereliyi

元件声明：
        component vga_controller_stream is
        port(
        address:IN std_logic;
        clk        :IN std_logic;
        reset :IN std_logic;
        chipselect:        IN std_logic;
        enwrite: IN std_logic;
        writedata:in std_logic_vector(7 downto 0);
        readyfordata: out std_logic;
        endofpacket ut std_logic;
        hsync:        out std_logic;
        vsync:        out std_logic;
        rgb:                out std_logic_vector(7 downto 0)
        );
错误行：
DUT : vga_controller_stream PORT MAP(address => address, clk => clk, reset => reset,chipselect => chipselect,enwrite => enwrite,writedata => writedata,readyfordata => readyfordata,endofpacket => endofpacket,hsync => hsync,vsync => vsync, rgb => rgb);

顶层文件为verilog的：
接口说明为：
module vga_controller_stream(
        clk,reset,chipselect,enwrite,writedata,readyfordata,endofpacket,address,hsync,vsync,rgb);
        input address;
        input clk;
        input reset;
        input chipselect;
        input enwrite;
        input[7:0] writedata;
        output readyfordata;
        output endofpacket;
        output hsync;
        output vsync;
        output[7:0] rgb;
       
没有问题吧！！？

pcalexhero

我ms也遇到过相同的问题

jiereliyi

你怎么解决的呢？

pychip

检查一下格式是否有问题，如果你的帖子是直接copy你的代码，看看这里：

endofpacket: out std_logic;

jiereliyi

这里没有错误。

asyou

有没有Verilog和VHDL混用啊！