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大家好,小弟现在有一棘手问题求助于各位高手,麻烦各位高手帮忙,先谢谢了。叙述如下:
clk_usart是外部输入时钟,clk_cnt32[4]是由clk_usart经32分频后的时钟(计数器分频),clk_cnt20[3]是由clk_cnt32[4]经20分频后的时钟(计数器分频),clk_usart_div2是由clk_usart经2分频后的时钟,在用design compiler 进行综合时,我写的部分脚本如下:
create_clock -period 10 -waveform {0 5} clk_usart
set_clock_latency 0.1 clk_usart
set_clock_uncertainty -setup 0.5 clk_usart
set_clock_uncertainty -hold 0.2 clk_usart
set_clock_transition 0.3 clk_usart
set_dont_touch_network clk_usart
create_generated_clock -name clk_cnt32[4] -source clk_usart -divide_by 32 [get_pins clk_cnt32_reg[4]/Q]
create_generated_clock -name clk_cnt20[3] -source [get_attribute [get_clocks clk_cnt32[4]] sources] -master_clock clk_cnt32[4] -divide_by 20 [get_pins clk_cnt20_reg[3]/Q]
create_generated_clock -name clk_usart_div2 -source clk_usart -divide_by 2 [get_pins clk_usart_div2_reg/Q]
set_dont_touch_network clk_cnt20[3]
set_dont_touch_network clk_cnt32[4]
set_dont_touch_network clk_usart_div2
综合时出现如下警告,该如何处理呢:
Warning: A non-unate path in clock network for clock 'clk_cnt32[4]'
from pin 'add_16/*cell*12/Y' is detected. (TIM-052)
Warning: A non-unate path in clock network for clock 'clk_cnt20[3]'
from pin 'add_24/U1_1_3/S' is detected. (TIM-052)
Warning: A non-unate path in clock network for clock 'clk_cnt20[3]'
from pin 'add_24/*cell*56/Y' is detected. (TIM-052)
Warning: A non-unate path in clock network for clock 'clk_cnt32[4]'
from pin 'add_16/*cell*12/Y' is detected. (TIM-052)
Warning: A non-unate path in clock network for clock 'clk_cnt20[3]'
from pin 'add_24/U1_1_3/S' is detected. (TIM-052)
Warning: A non-unate path in clock network for clock 'clk_cnt20[3]'
from pin 'add_24/*cell*56/Y' is detected. (TIM-052) |
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