一起来了解一下吧－目前为止所有razavi出过的书

semico_ljj

	Fundamentals of Microelectronics (Preliminary Edition), Behzad Razavi. John Wiley and Sons, 2006.
•	Phase-Locking in High Performance Systems (B. Rezavi, editor). IEEE Press, 2003
•	Design of Integrated Circuits for Optical Communication Systems, B. Razavi.  McGraw-Hill, 2003.
•	High-Speed CMOS Circuits for Optical Receivers, J. Savoj and B. Razavi. Boston: Kluwer Publishers, 2001
•	Design of Analog CMOS Integrated Circuits, Behzad Razavi. Boston: McGraw-Hill, c2000. Series: McGraw-Hill Series in Electrical and Computer Engineering.
•	RF Microelectronics, Behzad Razavi. Prentice Hall, c1998. Series: Prentice-Hall Communications Engineering & Emerging Technologies Series.
•	Monolithic Phase-locked Loops and Clock Recovery Circuits: Theory and design (B. Razavi, editor). New York: IEEE Press, c1996.
•	Principles of Data Conversion System Design, Behzad Razavi. New York: IEEE Press, c1995

[ 本帖最后由 semico_ljj 于 2006-11-22 15:21 编辑 ]

semico_ljj

IEEE2006  RAZAVI最新论文
CMOS Transceivers for the 60-GHz Band

by
Behzad Razavi
Electrical Engineering Department
University of California, Los Angeles

Abstract
Abstract
This paper gives an overview of millimeter-wave CMOS
transceiver design and presents several critical building
blocks operating around 60 GHz. A direct-conversion receiver
front end employing new LNA and mixer topologies
is described that exploits resonance by means of folded
microstrips Also, a direct-conversion transmitter incorporating
an on-chip dipole antenna is introduced that paves
the way for beamforming and MIMO systems. Finally,
a new phase-locked frequency divider is described that,
unlike its injection-locked counterparts, maintains a constant
phase noise across the input frequency range. The
circuits have been fabricated in standard 0.13-um
CMOStechnology. Experimental results for each prototype are
presented.

semico_ljj

IEEE 2006

A 60-GHz CMOS Receiver Front-End

by
Behzad Razavi, Fellow, IEEE

Abstract—The unlicensed band around 60 GHz can be utilized
for wireless communications at data rates of several gigabits per
second. This paper describes a receiver front-end that incorporates
a folded microstrip geometry to create resonance at 60 GHz in a
common-gate LNA and active mixers. Realized in 0.13- m CMOS
technology, the receiver front-end provides a voltage gain of 28 dB
with a noise figure of 12.5 dB while consuming 9 mWfrom a 1.2-V
supply.
Index Terms—LNAs, millimeter wave circuits, mixers, RF
CMOS, transceivers, transmission lines, 60-GHz band.

semico_ljj

Biography
Behzad Razavi received the BSEE degree from Sharif University of Technology in 1985 and the MSEE and PhDEE degrees from Stanford University in 1988 and 1992, respectively. He was with AT&T Bell Laboratories and Hewlett-Packard Laboratories until 1996. Since 1996, he has been Associate Professor and subsequently Professor of electrical engineering at University of California, Los Angeles. His current research includes wireless transceivers, frequency synthesizers, phase-locking and clock recovery for high-speed data  communications, and data converters.
Professor Razavi was an Adjunct Professor at Princeton University from 1992 to 1994, and at Stanford University in 1995. He served on the Technical Program Committees of the International Solid-State Circuits Conference (ISSCC) from 1993 to 2002 and VLSI Circuits Symposium from 1998 to 2002. He has also served as Guest Editor and Associate Editor of the IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems, and International Journal of High Speed Electronics. Professor Razavi was also recognized as one of the top 10 authors in the 50-year history of ISSCC. He is an IEEE Distinguished Lecturer, a Fellow of IEEE, and the author of Principles of Data Conversion System Design (IEEE Press, 1995), RF Microelectronics (Prentice Hall, 1998) (translated in Chinese and Japanese), Design of Analog CMOS Integrated Circuits (McGraw-Hill, 2001) (translated in Chinese and Japanese), and Design of Integrated Circuits for Optical Communications (McGraw-Hill, 2003). He was the editor of Monolithic Phase-Locked Loops and Clock Recovery Circuits (IEEE Press, 1996), and Phase-Locking in High-Performance Systems (IEEE Press, 2003).

semico_ljj

A Study of Injection Pulling and Locking in Oscillators2003

by
Behzad Razavi
Electrical Engineering Department
University of Califomia, Los Angeles

Abstract
This paper presents an analysis that confers new insights
into injection pulling and locking of oscillators and the re-
duction of phase noiseunder locked condition. A graphical
interpretation of Adler’s equation predicts the behavior of
injection-pulled oscillators in time and frequency domains.
An identity derived from the phase and envelope equations
expresses the required oscillator nonlinearity across the
lock range.

fds

OK, so ..............

semico_ljj

by
Sherif Galal, Behzad Razavi
Electrical Engineering Department, University of California, Los Angeles, CA

References
[1] B. Kleveland, et al., ‘‘Distributed ESD Protection for High-Speed
Integrated Circuits,’’ IEEE Electron Device Letters, vol. 21, pp. 390-392,
Aug. 2000.
[2] Dennis L. Feucht, Handbook of Analog Circuit Design, San Diego:
Academic Press, 1990.
[3] JEDEC Standard JESD22-A114-B, ‘‘Electrostatic Discharge (ESD)
Sensitivity Testing Human Body Model,’’ JEDEC, 2000.
[4] EIA/JEDEC Standard Test Method A115-A, ‘‘Electrostatic Discharge
(ESD) Sensitivity Testing Machine Model (MM),’’ EIA/JEDEC, 1997.

semico_ljj

A Stabilization Technique for Phase-Locked Frequency Synthesizers

by
Tai-Cheng Lee and Behzad Razavi
Electrical Engineering Department
University of California, Los Angeles

Abstract
A stabilization technique is presented that relaxes the trade-
off between the settling speed and the magnitude of out-
put sidebands in phase-locked frequency synthesizers. The
method introduces a zero in the open-loop transfer func-
tion through the use of a discrete-time delay cell, obviat-
ing the need for resistors in the loop filter. A 2.4-GHz
CMOS frequency synthesizer employing the technique set-
tles in approximately 60 ps with 1-MHz channel spacing
while exhibiting a sideband magnitude of -58.7 dBc. De-
signed for Bluetooth applications and fabricated in a 0.25-
pm digital CMOS technology, the synthesizer achieves a
phase noise of -112 dBc/Hz at 1-MHz offset and consumes
20 mW from a 2.5-V supply.

rwoir

dingding

flushrat

期待第一本