求助ams仿真的过程报错

帅帅的飞鸽

完全照搬了论坛内的ams仿真过程，参考：【转载】使用Cadence AMS仿真器做数模混合仿真 - Analog/RF IC 设计讨论 - EETOP 创芯网论坛 (原名：电子顶级开发网) -
但是跑出来的结果却报错，很奇怪的是代码是没有问题的，报错信息提及了两个一个是我写的半加器，一个是软件本身的L2E模块
我的半加器代码如下：

module test_verilog (a,b,s,c1);
    input a;
    input b;
    output c1;
    output s;

    assign s = a ^ b;
    assign c1 = a & b;

endmodule

报错信息如下：


csi-xmsim - CSI: Cadence Support Investigation, recording details
External Code in function: <unavailable> offset -65518
External Code in function: <unavailable> offset -65536
Verilog Syntax Tree: wire declaration (VST_D_WIRE) in module connectLib.L2E_2:module (VST)
        File: /home/eda/cadence/xcelium/2003/tools/affirma_ams/etc/connect_lib/L2E_2.vams, line 71, position 9
        Scope: L2E_2
        Decompile: logic Din
Verilog Syntax Tree: wire declaration (VST_D_WIRE) in module A_XYH.test_verilog:functional (VST)
        File: /home/temp5/Documents/smic18mserf_1833_1P6M_5Ia_1TMa2_MIM10_oa_cds_2019_01_24_v1.11_3/A_XYH/test_verilog/functional/verilog.v, line 7, position 12
        Scope: test_verilog
        Decompile: logic c1
        Source  :     output c1;
        Position:             ^
Error: Error processing stack frame(11) - skipping rest of frame!
Simulator Snap Shot: gd (SSS_GD) in snapshot A_XYH.test_full_adder:config (SSS)
Intermediate File: data block (IF_BLK) in snapshot A_XYH.test_full_adder:config (SSS)
Intermediate File: array of pointers (IF_PTRBLK) in snapshot A_XYH.test_full_adder:config (SSS)
Simulator Snap Shot: root (SSS_ROOT) in snapshot A_XYH.test_full_adder:config (SSS)
Intermediate File: root (IF_ROOT) in snapshot A_XYH.test_full_adder:config (SSS)
Simulator Snap Shot: dynlib (SSS_DYNLIB) in snapshot A_XYH.test_full_adder:config (SSS)
Simulator Snap Shot: dynpatch (SSS_DYNPATCH) in snapshot A_XYH.test_full_adder:config (SSS)
External Code in function: <unavailable> offset -65535
Intermediate File: string (IF_STRING) in snapshot A_XYH.test_full_adder:config (SSS)
        Decompile: /opt/XCELIUM_2003/tools/affirma_ams/lib/64bit/libamsvaluefetch
External Code in function: <unavailable> offset -65456
External Code in function: <unavailable> offset -65523
External Code in function: <unavailable> offset -32768
User Code in function: <unavailable> offset 33457284
csi-xmsim - CSI: investigation complete took 0.024 secs, send this file to Cadence Support



电路图如下：

帅帅的飞鸽

我已经解决了这个问题，通过设置另一种connect rule/Connect Module Based setup，并且指定E2L,和L2E,可以运行不报错

帅帅的飞鸽

有大神懂这个吗