Analog CMOS from 5 Micrometer to 5 Nanometer Sansen2015

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Analog CMOS from 5 Micrometer to 5 Nanometer S
The most important application of ICs, today, is most probably the Internet-ofThings. It involves sensor nodes and communications at the lowest-possiblepower levels. Similar low power levels are required for the next-generationsmart-phones as images and video become increasing requirements, inphone, body-worn, and automotive applications. Whatever technology is used,portability requires reduced power consumption.Analog CMOS in 5 Micrometer technologies dates from the seventies asshown by Moore’s Law (Figure 1.3.1). In early chips, Analog circuits weredominant; as time progressed, digital became more prevalent, such that at 5Nanometer it will overwhelm. Yet, Analog circuits traditionally establish theinterface to Digital. Thus, they must be realized in mainstream digital technologies, and correspondingly, are forced to conform to evolving Digital.Note that in Figure 1.3.1, the projections to 10nm and 5nm in 2016 and 2020,respectively, are highly dependent on the success of various competing technologies. Which of FinFETs [1,2], FD-SOI [1,2], SiGe [5], or other alternatives, ascends, is still a matter of current conjecture: A comparison willbe given in Figure 1.3.16 .Small channel lengths allow very high fT values, such as 300GHz at 28nm, and1.4THz at 10nm as shown in Figure 1.3.2. Velocity saturation has become themost dominant limitation. On the other hand, communication channels nowrequire linear amplifiers and filters of up to 100MHz, and more than 1GHz inthe near future. Note that these requirements are still low with respect to thehigh fT values potentially available. At the same time, relatively low baseband frequencies in combination with lowsupply voltage, will allow the transistors of analog baseband circuitry to operate in moderate or weak inversion. In the new EKV/BSIM6 models, theparameter Inversion Coefficient (IC) is used to measure how deep in weakinversion a MOS transistor operates. Moreover, an optimum operating regioncan be found, which depends on the actual channel length. This is examinedin the next Section 2.0 of this paper. Section 3.0 provides an overview of alldesign tricks used to reduce power consumption. Well-known examples arethe use of negative resistance and negative capacitance. Negative resistancescancel positive elements, thereby leading to lower power consumption. Alsonoise- and distortion-cancellation are discussed. Section 4.0 discusses digitally-assisted analog, especially for ADCs. Switching amplifiers are addedas well. Finally, in Section 5.0, an excursion is taken towards 5nm technologies: FinFET and FD-SOI realizations are compared down to 10nmchannel lengths. Vertical nanowire FETs are introduced down to 5nm. While,currently, a first inspection shows that only discrete devices can be used, it isencouraging to note that their I-V characteristics differ little from known ones.Further, it is demonstrated that conventional analog design techniques can stillbe adopted albeit at much higher frequencies.2.0 The Inversion Coefficient (IC) as a Design Parameter A single-transistor amplifier biased at {VGS-VT = 0.2V} yields a Gain-BandwidthCapacitance over Current product of about 1500MHzpF/mA [6]. This value of{VGS-VT} of 0.2V corresponds to an IC of about 10, as explained next.The transistor model used is the newly developed BSIM6 model, derived fromthe previous EKV model [7]. It still includes the well known Shichman-Hodgesmodel [8] in the mid-current region, but extends to weak inversion for low currents and velocity saturation for high currents. The current IDS is normalized to a specific value Ispec, which yields IC as indicated in Figure 1.3.3.The overdrive voltage {VGS-VT} is normalized as well, towards v (as noted onthe right side of Figure 1.3.3. Further, the relationship between v and IC (notedon the left side of the figure) is plotted in Figure 1.3.3. It is a very basic relationship, as it does not depend on the channel length, thus maintainingvalidity for 5nm V-FETs.The curve in Figure 1.3.3 also shows that negative values of {VGS-VT} are easilyobtained for low values of IC. For example, in Figure 1.3.4, the minimum supply voltage is shown versus GBW (Gain-Bandwidth Product) for a CMOSinverter amplifier, in which the minimum supply voltage equals 2VGS. Alreadyin 45nm CMOS, a 1GHz amplifier consisting of a simple CMOS inverter canhave a lower supply voltage than a 0.5V operational amplifier [9]. As a result,more and more amplifiers and filters in ADCs and other low-frequency circuits,replace operational amplifiers by CMOS inverters, which offer the advantagesof working at lower power levels and at lower supply voltages.The Inversion Coefficient (IC) is an excellent parameter for design. The curvesof the fTgm/IDS product are shown in Figure 1.3.5 [10]. This latter product combines speed, noise, and power consumption in one single Figure-Of-Merit.It is used for comparison of performance of many amplifiers including receiverLNAs. Further, it is the best FOM to guide analog designers in their choice ofthe biasing point of a transistor in the signal path.In Figure 1.3.5, it is shown that down to 65nm CMOS, the strong inversionregion is present in the middle with weak inversion on the left, and velocity saturation [6] on the right. In velocity saturation, the transconductance reaches its maximum value of WCoxVsat in which vsat is about 100km/s.However, in BSIM6 vsat is represented by λC = Lsat/L. This new parameter is thenormalized channel length in which Lsat is about 20nm. The cross-over valueof IC between strong inversion and velocity saturation is reached for IC = 1/(λC)2. For 65nm CMOS, λC is about 0.3 and this cross-over value isabout 10. When IC = 1, the value of fT is fTspec. It is clear from the curves onFigure 1.3.5 that several important observations can be made, as a result ofusing IC rather than {VGS-VT}. Thus, it is clear at 65nm that the optimum biasing values of IC are between 1 and 10. For lower values of IC, fT decreasesconsiderably, whereas for higher values than 10, the gm/IDS goes down steeply.For various channel lengths, the optimum values of IC shift to even deeperweak inversion. Thus, for 20nm CMOS, the optimum IC is still unity but for5nm CMOS the optimum IC decreases to about 0.06. The corresponding values of λC and fTspec are given as well (at the upper right of Figure 1.3.5). Notethat for smaller channel lengths, the maximum fTgm/IDS product increases andreaches about 22THz/V for 20nm CMOS. Also note that high values of thefTgm/IDS product cannot be reached for high IC (or VGS-VT) values. The limit isabout 22THz/V at IC = 1. This limit is independent of the p