请教一下仿真报错的问题

大桐桐

同样的用verilog写的symbol，左边电路仿真就没报错，右边就在报错，请教一下这个报错怎么解决
报错如下：ERROR (SFE-23):": The instance 'I6' is referencing an undefined model or subcircuit, DAC8ieal__veriloga'.
Either include the file containing the definition of DAC8ieal__veriloga', or define DAC8ieal__veriloga' before running the simulation.

                               
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