请教一下用verilog写了个symbol进行数模混仿，仿真报错verilog建的symbol未定义

大桐桐

                               
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以前也是用的这个symbol在跑仿真，现在跑不知为何报错了，报错提示如下：ERROR："adc8_presin_tran_sine/adexl_pre/results/data/Interactive.42/1/tran/netlist/netlist.
vams"41: The instance 'I6' is referencing an undefined model or subcircuit,DAC8ieal veriloga'.
Either include DAC8ieal__veriloga', or define DAC8ieal__veriloga' before running the simulation.
file containing he definition of