vcs三步法elab时出错

mengzhibb · 发表于 2024-11-10 18:19:07

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本帖最后由 mengzhibb 于 2024-11-15 22:31 编辑

背景：
尝试使用VCS三步法运行dut，elab时遇到如下错误:
Back to file '/home/synopsys/vcs/0-2018.09-SP2/etc/uvm-1.2/reg/uvm_reg_model.svh*
Parsing included file /home/synopsys/vcs/0-2018.09-SP2/etc/uvm-1.2/reg/snps_uvm_reg_bank.svh'
Back to file '/home/synopsys/vcs/0-2018.09-SP2/etc/uvm-1.2/reg/uvm_reg_model.svh.
Back to file '/home/synopsys/vcs/0-2018.09-SP2/etc/uvm-1.2/uvm_pkg.sv'.
Error-[TMENF-ILL] Top Module/Entity not found
Top module/entity/config "top_tb" is not found in the following library
list.
Liblist: work
1 warning
1 error
CPU time: 1.023 seconds to compile
make: *** [Makefile:77: elab] Error 255
==============makefile===========

VL0GAN =vlogan -full64 +v2k-sverilog -override_timescale=lps/1ps-kdb -lca
RTL _CMP_OPTS :=-ntb_opts uvm-1.2 -error=noMPD -l ./$(mode)/log/vlogan_design.log $(rtl_filelist)
UVM_CMP_OPTS := -ntb_opts uvm-1.2 -1 ./$(mode)/log/vlogan_cmp_uvm. log
TB CMP_OPTS:=-ntb_opts uvm-1.2-f $(tb_filelist)+incdir+$(UVM_HOME)/src -l ./$(mode)/log/vlogan_tb.log
ELAB :=vcs -kdb -full64 -sverilog +v2k -lca -l $(log)/uvm_cmp.log -Mdir=./$(mode)/uvm test cmp \
-o ./$(mode)/uvm_test simv -ntb_opts uvm-1.2-override_timescale=1ps/1ps -LDFLAGS -Wl,--no-as-needed -top top_tb
dcmp:
$(VLOGAN)$(RTL_CMP_OPTS)
vcmp:
$(VLOGAN) $(UVM_CMP_OPTS)
$(VLOGAN) $(TB_CMP_OPTS)
acmp:dcmp vcmp
elab:
$(ELAB)
clean:
rm ./$(mode)/log ./$(mode)/wave ./$(mode)/work ./$(mode)/uvm* -rf

===============已经做过的尝试=====

1.编译都使用-full64

2.dut,uvm,tb单独编译，而且都编译成功

3.sim目录下添加了synopsys_sim.setup

mz@ubuntu:~/project/verification/uvm_book/sim$ cat synopsys_sim.setup

WoRK>default

default:./3step/work

网上找了一圈也没有找到解决的办法，期待网友的帮助