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发表于 2024-9-27 15:37:34
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您看看我写的代码,位宽处理有没有问题
//////
wire signed [7:0] byte3_a;
wire signed [7:0] byte2_a;
wire signed [7:0] byte1_a;
wire signed [7:0] byte0_a;
wire signed [7:0] byte3_b;
wire signed [7:0] byte2_b;
wire signed [7:0] byte1_b;
wire signed [7:0] byte0_b;
assign byte3_a [7:0] = data_in_a[31:24];
assign byte2_a [7:0] = data_in_a[23:16];
assign byte1_a [7:0] = data_in_a[15: 8];
assign byte0_a [7:0] = data_in_a[ 7: 0];
assign byte3_b [7:0] = data_in_b[31:24];
assign byte2_b [7:0] = data_in_b[23:16];
assign byte1_b [7:0] = data_in_b[15: 8];
assign byte0_b [7:0] = data_in_b[ 7: 0];
///////
wire signed [7:0] byte3_a_sgn;
wire signed [7:0] byte2_a_sgn;
wire signed [7:0] byte1_a_sgn;
wire signed [7:0] byte0_a_sgn;
wire signed [7:0] byte3_b_sgn;
wire signed [7:0] byte2_b_sgn;
wire signed [7:0] byte1_b_sgn;
wire signed [7:0] byte0_b_sgn;
assign byte3_a_sgn [7:0] = {sign_a && byte3_a[7] , byte3_a[6:0]};
assign byte2_a_sgn [7:0] = {sign_a && byte2_a[7] , byte2_a[6:0]};
assign byte1_a_sgn [7:0] = {sign_a && byte1_a[7] , byte1_a[6:0]};
assign byte0_a_sgn [7:0] = {sign_a && byte0_a[7] , byte0_a[6:0]};
assign byte3_b_sgn [7:0] = {sign_b && byte3_b[7] , byte3_b[6:0]};
assign byte2_b_sgn [7:0] = {sign_b && byte2_b[7] , byte2_b[6:0]};
assign byte1_b_sgn [7:0] = {sign_b && byte1_b[7] , byte1_b[6:0]};
assign byte0_b_sgn [7:0] = {sign_b && byte0_b[7] , byte0_b[6:0]};
/////
reg signed [15:0] mult_byte3;
reg signed [15:0] mult_byte2;
reg signed [15:0] mult_byte1;
reg signed [15:0] mult_byte0;
always@(...)begin
if(!rstn)begin
mult_byte3[15:0] <= 16'b0;
mult_byte2[15:0] <= 16'b0;
mult_byte1[15:0] <= 16'b0;
mult_byte0[15:0] <= 16'b0;
end
else if(mult_flag)begin
mult_byte3[15:0] <= byte3_a_sgn[7:0] * byte3_b_sgn[7:0] ;
mult_byte2[15:0] <= byte2_a_sgn[7:0] * byte2_b_sgn[7:0] ;
mult_byte1[15:0] <= byte1_a_sgn[7:0] * byte1_b_sgn[7:0] ;
mult_byte0[15:0] <= byte0_a_sgn[7:0] * byte0_b_sgn[7:0] ;
end
end
/////
reg signed [17:0] mult_byte_sum;
always@(...)begin
if(!rstn)
mult_byte_sum[17:0] <= 18'b0;
else if(mult_sum_flag)
mult_byte_sum[17:0] <= mult_byte3[15:0] +
mult_byte2[15:0] +
mult_byte1[15:0] +
mult_byte0[15:0];
end
/////
reg signed [31:0] sum;
always@(...)begin
if(!rstn)
sum[31:0] <= 32'b0;
else if(sum_flag)
sum[31:0] <= sum[31:0] + mult_byte_sum[17:0];
else
sum[31:0] <= 32'b0;
end
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