Prime Time User Guide 中英对照 第五章（上）

LunarJanuary

最近进到项目里面了，又找到一款好玩的游戏所以最近进度比较慢，不过观众也比较少所以也没关系啊哈哈。

话不多说，直接上马。

To learn about constraining the inputs and outputs of the design, see these topics:

• Timing Constraints

• Input Delays

• Output Delays

• Drive Characteristics at Input Ports

• Port Capacitance

• Wire Load Models

• Slew Propagation

• Design Rule Constraints

• Ideal Networks

• Checking the Constraints

Timing Constraints

Before you begin timing analysis, you need to specify the timing constraints on the design. A timing constraint (also called a timing assertion) limits the allowed range of time that a signal can arrive at a device input or be valid at a device output.在开始时序分析之前，您需要在设计上指定时序约束。时序约束（也称为timing assertion）限制了信号到达设备输入或在设备输出端有效所允许的时间范围。

Input Delays

To do constraint checking at the inputs of the design, the tool needs information about the arrival times of signals at the inputs. To specify the timing of external paths leading to an input port, use the set_input_delay command. The tool uses this information to check for timing violations at the input port and in the transitive fanout from that input port. With this command, you specify the minimum and maximum amount of delay from a clock edge to the arrival of a signal at a specified input port.

为了在设计的输入时进行约束检查，该工具需要有关信号在输入端的到达时间的信息。要指定通向输入端口的外部路径的时序，请使用 set_input_delay 命令。该工具使用此信息来检查输入端口和该输入端口的可传递扇出是否存在时序冲突。使用此命令，您可以指定从时钟边沿到信号到达指定输入端口的最小和最大延迟量。

Applying the set_drive or set_driving_cell commands to the port causes the port to have a cell delay that is the load-dependent value of the external driving-cell delay. To prevent this delay from being counted twice, estimate the load-dependent delay of the driving cell, then subtract that amount from the input delays on the port.

将 set_drive 或 set_driving_cell 命令应用于port会导致port具有cell delay，该延迟是外部驱动cell延迟的负载相关值。为防止此延迟被计算两次，估计驱动单元的负载相关延迟，然后从端口上的输入延迟中减去该值。

The input delay should equal the path length from the clock pin of the source flip-flop to the output pin of the driving cell, minus the load-dependent portion of the driving cell’s delay. The following example shows the external path for the L1 clock port to port IN1.

输入延迟应等于从源触发器的clock pin到驱动单元的output pin的路径长度，减去驱动单元延迟的负载相关部分。以下示例显示了 L1 clock port到 port IN1 的外部路径。

When you use the set_input_delay command, you can specify whether the delay value includes the network latency or source latency.

使用 set_input_delay 命令时，可以指定延迟值是包括network latency还是source latency。

Example 1

If the delay from L1 clock port to IN1 (minus the load-dependent delay of the driving cell) is 4.5, this set_input_delay command applies:

如果从 L1 clock port到 IN1 的延迟（减去驱动单元的负载相关延迟）为 4.5，则适用以下set_input_delay命令：

pt_shell> set_input_delay 4.5 -clock PHI1 {IN1}

Example 2

If paths from multiple clocks or edges reach the same port, specify each one using the -add_delay option. If you omit the -add_delay option, existing data is removed. For example:

如果来自多个时钟或边沿的路径到达同一端口，请使用 -add_delay 选项指定每个端口。如果省略 -add_delay 选项，则会删除现有数据。例如：

pt_shell> set_input_delay 2.3 -clock PHI2 -add_delay {IN1}

If the source of the delay is a level-sensitive latch, use the -level_sensitive option. This allows PrimeTime to determine the correct single-cycle timing constraint for paths from this port. Use the -clock_fall option to denote a negative level-sensitive latch; otherwise, the -level_sensitive option implies a positive level-sensitive latch.

如果延迟的源头是电平敏感锁存器，请使用 -level_sensitive 选项。这允许PrimeTime为来自此端口的路径测定正确的单周期时序约束。使用 -clock_fall 选项表示负电平敏感锁存器;否则，-level_sensitive 选项表示着一个正电平敏感锁存器。

To see input delays on ports, use the report_port -input_delay command.

To remove input delay information from ports or pins in the current design set using the set_input_delay command, use the remove_input_delay command. The default is to remove all input delay information in the port_pin_list option.

Using Input Ports Simultaneously for Clock and Data

PrimeTime allows an input port to behave simultaneously as a clock and data port. You can use the timing_simultaneous_clock_data_port_compatibility variable to enable or disable the simultaneous behavior of the input port as a clock and data port. When this variable is false, the default, simultaneous behavior is enabled and you can use the set_input_delay command to define the timing requirements for input ports relative to a clock. In this situation, the following applies:

PrimeTime允许输入端口同时充当时钟和数据端口。您可以使用timing_simultaneous_clock_data_port_compatibility 变量来启用或禁用输入端口作为时钟和数据端口的同时行为。当此变量为 false 时，将启用默认的并发行为，您可以使用 set_input_delay 命令定义输入端口相对于时钟的时序要求。在这种情况下，以下情况适用：

• If you specify the set_input_delay command relative to a clock defined at the same port and the port has data sinks, the command is ignored and an error message is issued. There is only one signal coming to port, and it cannot be at the same time data relative to a clock and the clock signal itself.

• 如果对同一port上定义的时钟声明 set_input_delay 命令，并且该port有data sinks，则忽略该命令并发出错误消息。只有一个信号进入port，并且不能同时是有关于时钟的数据和时钟信号本身。

• If you specify the set_input_delay command relative to a clock defined at a different port and the port has data sinks, the input delay is set and controls data edges launched from the port relative to the clock.

• 如果对在不同port上定义的时钟的声明 set_input_delay 命令，并且该port具有data sinks，则输入延迟被设上并控制数据边沿从相关与此时钟的port发射出去。

• Regardless of the location of the data port, if the clock port does not fanout to data sinks, the input delay on the clock port is ignored and you receive an error message.

• 无论data port的位置如何，如果clock port 未扇出到data sink，则clock port 上的输入延迟将被忽略，并且您会收到错误消息。

When you set the timing_simultaneous_clock_data_port_compatibility variable to true, the simultaneous behavior is disabled and the set_input_delay command defines the arrival time relative to a clock. In this situation, when an input port has a clock defined on it, PrimeTime considers the port exclusively as a clock port and imposes restriction on the data edges that are launched. PrimeTime also prevents setting input delays relative to another clock.

将 timing_simultaneous_clock_data_port_compatibility 变量设置为 true 时，将禁用并发行为，并且 set_input_delay 命令定义了关于clock的到达时间。在这种情况下，当输入port上定义了时钟时，PrimeTime将该port仅视为clock port，并对发送的数据沿施加限制。PrimeTime还可以防止设置对于另一个时钟的输入延迟。

To control the clock source latency for any clocks defined on an input port, you must use the set_clock_latency command.

要控制在输入端口上定义的任何clock的clock source latency，必须使用 set_clock_latency 命令。

Output Delays

To do constraint checking at the outputs of the design, the tool needs information about the timing requirements at the outputs. To specify the delay of an output port to a register, use the set_output_delay command.

为了在设计的outport进行约束检查，该工具需要有关outputs时序要求的信息。要指定寄存器到output port的延迟，请使用 set_output_delay 命令。

With this command, you specify the minimum and maximum amount of delay between the output port and the external sequential device that captures data from that output port. This setting establishes the times at which signals must be available at the output port to meet the setup and hold requirements of the external sequential element:

使用此命令，您可以指定输出端口与从该输出端口捕获数据的外部顺序设备之间的最小和最大延迟量。此设置确定信号必须在输出端口上可用的时间，以满足外部顺序元件的设置和保持要求：

• Maximum_output_delay = length_of_longest_path_to_register_data_pin + setup_time_of_the_register

• Minimum_output_delay = length_of_shortest_path_to_register_data_pin – hold_time

In the preceding example, this command sets an output delay of 4.3 relative to the rising edge of clock PHI1 on port OUT1:

在前面的示例中，以下命令将相对于端口 OUT1 上时钟 PHI1 的上升沿的输出延迟设置为 4.3，：

pt_shell> set_output_delay 4.3 -clock PHI1 {OUT1}

To show output delays associated with ports, use the report_port -output_delay command.

要显示与port关联的输出延迟，请使用 report_port -output_delay 命令。

To remove output delay from output ports or pins set through the set_output_delay command, use the remove_output_delay command. By default, all output delays on each object in the port or pin list are removed. To restrict the removed output delay values, use the -clock, -clock_fall, -min, -max, -rise, or -fall option.

要从通过 set_output_delay 命令设置的输出port或pin中删除输出延迟，请使用 remove_output_delay 命令。默认情况下，port或pin list中每个object的所有输出延迟都将被删除。要限制删除的输出延迟，请使用 -clock、-clock_fall、-min、-max、-rise 或 -fall 选项。

Drive Characteristics at Input Ports

To accurately time a design, you need to define the drive capability of the external cell driving each input port.

为了准确地确定设计时序，您需要定义驱动每个input port的外部cell的驱动能力。

PrimeTime uses this information to calculate the load-dependent cell delay for the port and to produce an accurate transition time for calculating cell delays and transition times for the following logic stages.

PrimeTime使用此信息来计算port的load-dependent cell delay并生成准确的transition time用于计算后续各级逻辑的cell延迟和transition time。

The set_driving_cell command can specify a library cell arc for the driving cell so that timing calculations are accurate even if the capacitance changes. This command causes the port to have the transition time calculated as if the given library cell were driving the port.

set_driving_cell 命令可以为driving cell指定库cell arc，即使电容发生变化，也能准确计算时序。此命令使此port计算过转换时间，如同指定的库cell正在驱动此port一样。

For less precise calculations, you can use the set_drive or set_input_transition command. The most recent drive command has precedence. If you issue the set_drive command on a port and then use the set_driving_cell command on the same port, information from the set_drive command is removed.

对于不太精确的计算，可以使用 set_drive 或 set_input_transition 命令。最新的drive command优先权最高。如果对一个port上使用 set_drive 命令，然后在同一port上使用 set_driving_cell 命令，则会删除 set_drive 命令中的信息。

Setting the Port Driving Cell

The set_driving_cell command directs PrimeTime to calculate delays as though the port were an instance of a specified library cell. The port delay is calculated as a cell delay that consists of only the load-dependent portion of the port.

set_driving_cell命令指示 PrimeTime 计算延迟就像此port是指定的一个库 cell 的实例一样。此port的延迟被计算成仅包含port的负载相关部分的cell delay。

The transition time for the port is also calculated as though an instance of that library cell were driving the net. The delay calculated for a port with information from the set_driving_cell command takes advantage of the actual delay model for that library cell, whether it is nonlinear or linear. The input delay specified for a port with a driving cell or drive resistance should not include the load-dependent delay of the port.

port的transition time也被计算，就像该库单元的实例正在drive此net。使用 set_driving_cell 命令中的信息为计算port的延迟用到了该库单元的实际延迟模型，无论是非线性的还是线性的。为具有驱动单元或驱动电阻的port指定的输入延迟不应包括port的负载相关延迟。

To display port transition or drive capability information, use the report_port command with the -drive option.

要显示port transition或驱动能力信息，请使用带有 -drive 选项的 report_port 命令。

With the set_driving_cell command you can specify the input rise and fall transition times for the input of a driving cell using the -input_transition_rise or the -input_transition_fall option. If no input transition is specified, the default is 0.

使用 set_driving_cell 命令，您可以使用 -input_transition_rise 或 -input_transition_fall 选项指定驱动单元输入的输入上升和下降 transition time。如果未指定input transition，则默认为 0。

Setting the Port Drive Resistance

The set_drive command defines the external drive strength or resistance for input and inout ports in the current design. In the presence of wire load models, the transition time and delay reported for the port are equal to Rdriver * Ctotal. PrimeTime uses this transition time in calculating the delays of subsequent logic stages.

set_drive 命令定义当前设计中input和inout port的外部驱动强度或电阻。在存在电线负载模型的情况下，从port报告的transition time和延迟等于 Rdriver * Ctotal。PrimeTime使用此transition time来计算后续逻辑级的延迟。

You can use the set_drive command to set the drive resistance on the top-level ports of the design when the input port drive capability cannot be characterized with a cell in the logic library. However, this command is not as accurate for nonlinear delay models compared to the set_driving_cell command. The set_drive command is useful when you cannot specify a library cell (for example, when the driver is a custom block not modeled as a Synopsys library cell).

您可以使用 set_drive 命令在design的top-level port上设置驱动电阻，当输入端口驱动能力无法用逻辑库中的单元进行表征时。但是，与set_driving_cell命令相比，此命令对于非线性延迟模型并不准确。当无法指定库单元时（例如，当驱动程序是未建模为 Synopsys 库单元的自定义块时），set_drive 命令非常有用。

Setting a Fixed Port Transition Time

The set_input_transition command defines a fixed transition time for input ports. The port has zero cell delay. PrimeTime uses the specified transition time only in calculating the delays of logic driven by the port.

set_input_transition 命令定义输入端口的固定转换时间。该端口具有零cell延迟。PrimeTime仅在计算端口驱动的逻辑延迟时使用指定的转换时间。

A fixed transition time setting is useful for

固定转换时间设置可用于

• Comparing the timing of a design to another tool that supports only input transition time.

• 将design的时序与仅支持输入转换时间的另一种工具进行比较。

• Defining transition for ports at the top level of a chip, where a large external driver and a large external capacitance exist. In this case, the transition time is relatively independent of capacitance in the current design.

• 定义芯片顶层端口的转换时间，存在大型外部驱动器和大型外部电容。在这种情况下，转换时间与当前design中的电容相对无关。

Displaying Drive Information

To display drive information, you can use the report_port command with the -drive option.

要显示驱动信息，可以将 report_port 命令与 -drive 选项一起使用。

Removing Drive Information From Ports

To remove drive information from ports, use the following commands.

要从端口中删除驱动信息，请使用以下命令。

Port Capacitance

To accurately time a design, you need to describe the external load capacitance of nets connected to top-level ports, including the pin and wire capacitances, by using the set_load command.

为了准确确定design时序，您需要使用 set_load 命令描述连接到顶层端口的网络的外部负载电容，包括引脚和导线电容。

Example 1

To specify the external pin capacitance of ports, enter

要指定端口的外部引脚电容，请输入

pt_shell> set_load -pin_load 3.5 {IN1 OUT1 OUT2}

You also need to account for wire capacitance outside the port. For prelayout, specify the external wire load model and the number of external fanout points. This process is described in Setting Wire Load Models Manually.

您还需要考虑端口外部的线间电容。对于预布局，请指定外部线负载模型和外部扇出数。手动设置线负载模型中介绍了此过程。

Example 2

For postlayout, specify the external annotated wire capacitance as wire capacitance on the port. For example:

pt_shell> set_load -wire_load 5.0 {OUT3}

To remove port capacitance values, use the remove_capacitance command.

Wire Load Models

To accurately calculate net delays, PrimeTime needs information about the parasitic loads of the wire interconnections. Before placement and routing have been completed, PrimeTime estimates these loads by using wire load models provided in the logic library.

为了准确计算net delay，PrimeTime需要有关互连线的寄生负载的信息。在完成放置和布线之前，PrimeTime使用逻辑库中提供的线负载模型来估计这些负载。

Logic library vendors supply statistical wire load models to support estimating wire loads based on the number of fanout pins on a net. You can set wire load models manually or automatically.

逻辑库供应商提供统计学线负载模型，以支持根据net上的扇出引脚数估算线负载。您可以手动或自动设置线负载模型。

Setting Wire Load Models Manually

To manually set a named wire load model on a design, instance, list of cells, or list of ports, use the set_wire_load_model command.

For example, consider this design hierarchy:

To set a model called 10x10 on instances of BOTTOM, a model called 20x20 on instances of MID, and a model called 30x30 on nets at the top level, use these commands:

pt_shell> set_wire_load_mode enclosed

pt_shell> set_wire_load_model -name 10x10 \

[all_instances BOTTOM]

pt_shell> set_wire_load_model -name 20x20 \

[all_instances MID]

pt_shell> set_wire_load_model -name 30x30

To capture the external part of a net that is connected to a port, you can set an external wire load model and a number of fanout points. For example, to do this for port Z of the current design:

为了计算连接到port的net的外部部分，可以设置外部线负载模型和扇出点的数量。例如，对当前design的port Z做这些

pt_shell> set_wire_load_model -name 70x70 [get_ports Z]

pt_shell> set_port_fanout_number 3 Z

To calculate delays, PrimeTime assumes that port Z has a fanout of 3 and uses the 70x70 wire load model.

为了计算延迟，PrimeTime假设端口Z的扇出为3，并使用名为70x70线负载模型。

To see wire load model settings for the current design or instance, use the report_wire_load command. To see wire load information for ports, use the report_port command with -wire_load option. To remove user-specified wire load model information, use the remove_wire_load_model command.

要查看当前design或实例的线负载模型设置，请使用 report_wire_load 命令。要查看端口的线负载信息，请使用带有 -wire_load 选项的 report_port 命令。要删除用户指定的线负载模型信息，请使用 remove_wire_load_model 命令。

Automatic Wire Load Model Selection

PrimeTime can set wire loads automatically when you update the timing information for your design. If you do not specify a wire load model for a design or block, PrimeTime automatically selects the models based on the wire load selection group, if specified.

当您更新design的时序信息时，PrimeTime可以自动设置线负载。如果未为design或block指定线负载模型，PrimeTime会根据线负载选型组（如果指定）自动选择模型。

If you do not apply a wire load model or selection group but the library defines a default_wire_load model, PrimeTime applies the library-defined model to the design. Otherwise, the values for wire resistance, capacitance, length, and area are all 0.

如果您不应用线负载模型或选型组，但库定义了default_wire_load模型，则PrimeTime会将库定义的模型应用于design。否则，导线电阻、电容、长度和面积的值均为 0。

Automatic wire load selection is controlled by selection groups, which map the block sizes of the cells to wire load models. If you specify the set_wire_load_selection_group command on the top design, or if the main logic library defines a default_wire_load_selection_group, PrimeTime automatically enables wire load selection.

自动选择线负载由选型组控制，将单元的block大小映射到线负载模型。如果在top design上指定set_wire_load_selection_group命令，或者如果主逻辑库定义了default_wire_load_selection_group，则PrimeTime会自动启用线负载选型。

When wire load selection is enabled, the wire load is automatically selected for hierarchical blocks larger than the minimum cell area, based on the cell area of the block.

启用线负载选型后，将根据块的单元面积自动为大于最小单元面积的分层块选择导线负载。

To set the minimum block size for automatic wire load selection, enter

pt_shell> set_wire_load_min_block_size size

In this command, size is the minimum block size for automatic wire load selection, in library cell area units. The specified size must be greater than or equal to 0.

在此命令中，size 是自动选取线负载的block的最小值，以库单元面积为单位。指定的size必须大于或等于 0。

The auto_wire_load_selection environment variable specifies automatic wire load selection. The default setting is true, enabling automatic wire load selection if a selection group is associated with the design. To disable automatic wire load selection, enter

auto_wire_load_selection环境变量指定自动线负载选型。默认设置为 true，如果选型组与design相关联，则启用自动线负载选型。要禁用自动线负载选型，请输入

pt_shell> set auto_wire_load_selection false

To remove the wire load selection group setting, use the remove_wire_load_selection_group command.

Setting the Wire Load Mode

The current wire load mode setting, which can be set with the set_wire_load_mode command, determines the wire load models used at different levels of the design hierarchy. There are three possible mode settings: top, enclosed, or segmented.

当前的线负载模型设置，可使用 set_wire_load_mode 命令进行设置，决定了在不同设计层次结构级别使用的线负载模型。有三种可能的模式设置： top, enclosed, or segmented.

If the mode for the top-level design is top, the top-level wire load model is used to compute wire capacitance for all nets within the design, at all levels of hierarchy. If the mode for the top-level design is either enclosed or segmented, wire load models on hierarchical cells are used to calculate wire capacitance, resistance, and area for nets inside these blocks.

如果top-level design的模式为top，则顶层线负载模型用于计算design中所有层级所有net的线间电容。如果顶层design的模式是enclosed or segmented的，则使用hierarchical cells上的线负载模型来计算这些block内net的线间电容、电阻和面积。

If the enclosed mode is set, PrimeTime determines net values using the wire load model of the hierarchical cell that fully encloses the net. If the segmented mode is set, PrimeTime separately determines net values for segments of the net in each level of hierarchy, and then obtains the total net value from the sum of all segments of the net.

如果设置了 enclosed模式，PrimeTime将使用完全encloses net的hierarchical cell的线负载模型确定净值。如果设置了segmented 模式，PrimeTime将分别确定每个层次结构中net的净值，然后将其总和得到总净值。

If you do not specify a mode, the default_wire_load_mode setting of the main logic library is used. The enclosed mode is often the most accurate. However, your ASIC vendor might recommend a specific mode.

如果未指定模式，则使用主逻辑库的default_wire_load_mode设置。 enclosed模式通常是最准确的。但是，您的 ASIC 供应商可能会推荐特定模式。

To set the wire load mode to enclosed on the current design, enter

pt_shell> set_wire_load_mode enclosed

This design example sets the following wire load models:

set_wire_load_model -name Big (the current design)

set_wire_load_model -name Medium (instances U1 and U2)

set_wire_load_model -name Small (instance U2/U1)

The following table lists the resulting wire load modes and models that apply to the nets in the design example.

下表列出了适用于design示例中net的线负载模式和模式。

Reporting Wire Load Models

To obtain wire load reports from PrimeTime, use these commands:

要从PrimeTime获取线负载报告，请使用以下命令：

• report_wire_load

• report_port -wire_load

Slew Propagation

At a pin where multiple timing arcs meet or merge, PrimeTime computes the slew per driving arc at the pin, then selects the worst slew value at the pin to propagate along. Note that the slew selected might not be from the input that contributes to the worst path, so the calculated delay from the merge pin could be pessimistic.

在多个timing arc 相遇或融合的pin，PrimeTime计算此pin的每一个driving arc的slew，然后选择此pin最差的slew进行传播，注意所选的slew可能不是来自导致最差路径的输入，因此从合并引脚计算出的延迟可能是悲观的。

Minimum slew propagation is similar to maximum slew propagation. In other words, PrimeTime selects minimum slew based on the input with the best delay at the merge point.

最小slew传播类似于最大slew传播。换句话说，PrimeTime会根据合并点处具有最小延迟的输入来选择最小slew。

Design Rule Constraints

PrimeTime checks for violations of design rule constraints that are defined in the library or by PrimeTime commands. These rules include

• Maximum limit for transition time

• Maximum and minimum limits for capacitance

• Maximum limit for fanout

To report design rule constraint violations in a design, use the report_constraint command.

Maximum Transition Time

The maximum transition time in PrimeTime is treated in a similar fashion as the slew. In this topic, slew is first discussed in the context of thresholds and derating, then the discussion is extended to maximum transition time.

PrimeTime 中的最大转换时间的处理方式与slew类似。在本主题中，首先在 context of thresholds and derating背景下讨论回转，然后讨论扩展到最大转换时间。

You can represent a SPICE waveform as a floating-point number in Liberty tables. In the following figure,

你可以在 Liberty 表中将 SPICE 波形表示为浮点数。在下图中，

• SPICE waveform is measured 10-90

• SPICE waveform is showing in blue line

• SPICE measured transition time with slew threshold 10-90 is 10 ps

• Linearized waveform measuring transition time with slew threshold 0-100 is 12.5 ps = 10 * (100-0) / (90-10)

• Representation as single float with slew threshold 30-70 is 5 ps = 12.5 * (70-30) / (100-0)

The SPICE waveform can thus be represented as a floating-point number in Liberty tables or in PrimeTime report as follows:

因此，SPICE波形可以在Liberty表或PrimeTime报告中表示为浮点数，如下所示：

• A: 10-ps slew threshold as 10-90 with slew derating 1.0

• B: 12.5-ps slew threshold as 10-90 with slew derating 0.8

• C: 5-ps slew threshold as 10-90 with derating 2.0

Note that slew threshold in library is always the threshold used for SPICE measurement. Case A is the native representation, measured in Liberty. Cases B and C are rescaled to the slew threshold 0-100 and 30-70, respectively.

请注意，库中的slew threshold始终是用于SPICE测量的阈值。案例 A 是自然表示，在 Liberty 中测量。案例 B 和 C 分别重新调整到slew阈值 0-100 和 30-70。

Multiple Threshold and Derating Values in Libraries

Liberty allows an arbitrary slew threshold to minimize the error due to slew linearization for various process technologies. Therefore, whenever slew information from a library interacts with another library (or even a pin of the same library with different slew threshold), a conversion to a common base is required.

Liberty 允许任意slew阈值，以最大程度地减少由于各种工艺技术的slew线性化而产生的误差。因此，每当来自一个库的slew信息与另一个库（甚至是同一pin具有不同slew阈值的同一库）交互时，都需要转换为公共基础。

Assume that you have a library L1 with thresholds TL1-TH1, derate SD1, and L2 with TL2-TH2, derate SD2. Note that L1, L2 are just entities that have their own local thresholds, such as library, design, and library pin.

假设您有一个阈值为 TL1-TH1 的库 L1，derate SD1 ，而 L2 具有 TL2-TH2，derate SD2 。请注意，L1、L2 只是具有自己的本地阈值的实体，例如库、设计和库引脚。

Assume S1 - slew in local thresholds and a derate of L1, and S2 - slew in local thresholds and a derate of L2. The same conversion rule applies if maximum transition is considered instead of slews.

假设 S1 - slew在局部阈值中，derate为 L1，S2 - slew在局部阈值中，derate为 L2。如果考虑最大ansition而不是slew rate，则相同的转换规则也适用。

You can then obtain slews expressed in the local thresholds and derate of the other object as follows:

Equivalent slew S2_1, which is slew S2 expressed in the local derate /threshold of L1:

S2_1 = S2 * (SD2 / (TH2 - TL2)) * ((TH1 - TL1)/ SD1)

The meaning of S2_1 is a float number that represents a waveform of slew S2 but measured in the context of L1. The S1 and S2_1 can be directly compared; the S1 and S2 cannot.

S2_1 的含义是表示slew S2 的波形一个浮点数，但在 L1 的上下文中测量。S1 和 S2_1 可以直接比较;S1 和 S2 不能。

Note that in the presence of detailed RC, slew is computed appropriately in the context of threshold and derate.

请注意，在存在详细 RC 的情况下，slew是在阈值和降额的环境下被合理计算的。

To learn how maximum transition constraint is handled in the context of thresholds and derate, see Specifying the Maximum Transition Constraint.

Specifying the Maximum Transition Constraint

Maximum transition constraints can come from a user input, library, and library pin. User-specified maximum transition constraints are expressed with the main library derate and slew threshold of PrimeTime.

最大转换约束可以来自用户输入、库和库引脚。用户指定的最大转换约束用 PrimeTime 的main library derate和 slew threshold表示。

The set_max_transition command sets a maximum limit on the transition time for all specified pins, ports, designs, or clocks. When specified on clocks, pins in the clock domain are constrained. Within a clock domain, you can optionally restrict the constraint further to only clock paths or data paths, and to only rising or falling transitions.

set_max_transition 命令为所有指定的引脚、端口、design或clock设置转换时间的最大限制。在clock上指定时，clock domain中的引脚受到约束。在clock domain中，您可以选择将约束进一步限制为仅clock path或data path，以及仅上升或下降transitions。

By default, during constraint checking on a pin or port, the most restrictive constraint specified on a design, pin, port, clock (if the pin or port is in that clock domain), or library is considered. This is also true where multiple clocks launch the same path.

默认情况下，在对引脚或端口进行检查期间约束时，将考虑在design、引脚、端口、时钟（如果引脚或端口位于该时钟域中）或库上指定的最严格约束。当多个时钟启动同一路径时也是如此。

To change the default behavior, set the timing_enable_max_slew_precedence to true. In that case, where the constraint is set determines the priority, irrespective of the relative constraint values, as follows:

若要更改默认行为，请将timing_enable_max_slew_precedence设置为 true，在这种情况下，设置约束的优先级的绝对位置，而不考虑相对约束值，如下所示：

• Pin or port level
• Library-derived constraint
• Clock or design level
  

The set_max_transition command places the max_transition attribute, which is a design rule constraint, on the specified objects. In PrimeTime, the slews and maximum transition constraint attributes are reported in the local threshold and derate of each pin or library. For example, the maximum transition time set in the context of the design threshold and derate is scaled to that of the design pin's threshold and derate. The scaling of transition time for slew threshold is on by default.

set_max_transition 命令将 max_transition 属性（是design rule约束的）置于指定的对象上。在PrimeTime中，slew和最大transition约束属性在每个引脚或库的局部阈值和detate中报告。例如，最大转换时间在design阈值的context 中设置，derate按design引脚的阈值和derate进行缩放。默认情况下，slew阈值的transition 时间缩放处于打开状态。

To apply a global derating factor to max_transition values, set the timing_max_transition_derate variable.

若要将全局derating factor应用于max_transition值，请设置 timing_max_transition_derate 变量。

To see the capacitance constraint evaluations, run the report_constraint -max_capacitance command. To see port capacitance limits, run the report_port -design_rule command. To see the default capacitance settings for the current design, run the report_design command. To remove user-specified capacitance limits, run the remove_max_capacitance command.

要查看电容约束计算，请运行 report_constraint -max_capacitance 命令。要查看端口电容限制，请运行 report_port -design_rule 命令。要查看当前design的默认电容设置，请运行 report_design 命令。要删除用户指定的电容限制，请运行 remove_max_capacitance 命令。

Evaluating the Maximum Transition Constraint

To view the maximum transition constraint evaluations, use the report_constraint -max_transition command.

要查看最大transition约束计算，请使用 report_constraint -max_transition 命令。

PrimeTime reports all constraints and slews in the threshold and derate of the pin of the cell instance, and the violations are sorted based on the absolute values (that is, they are not expressed in that of design threshold and derate). You can also use the report_constraint command to report constraint calculations only for maximum capacitance and maximum transition for a specified port or pin list. Use the object_list option to specify a list of pins or ports in the current design that you want to display constraint related information.

PrimeTime报告cell instance引脚的所有约束和阈值中的slews和derate，并根据绝对值对违例进行排序（即，它们不以design阈值和derate表示）。您还可以使用 report_constraint 命令仅报告指定端口或引脚列表的最大电容和最大转换的约束计算方法。使用 object_list 选项指定当前design中要显示约束相关信息的引脚或端口列表。

To see the port maximum transition limit, use the report_port -design_rule command. To see the default maximum transition setting for the current design, use the report_design command. To undo maximum transition limits previously set on ports, pins, designs, or clocks, use remove_max_transition.

要查看端口最大转换限制，请使用 report_port -design_rule 命令。要查看当前design的默认最大transition设置，请使用 report_design 命令。要撤消之前在端口、引脚、design或clock上设置的最大transition限制，请使用 remove_max_transition。

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