还有这篇: https://ieeexplore.ieee.org/document/10052667 A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue AmplifiersPublished in: IEEE Access ( Volume: 11) Page(s): 22531 - 22541 Date of Publication: 24 February 2023 Electronic ISSN: 2169-3536
A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic
A Wide Input Common-mode Range Pipelined ADC Front-end with Common-mode