LVS仿真电容电阻始终过不了

MISU · 发表于 2024-5-31 14:10:17

飞翔的鸟发表于 2024-5-31 13:54
你目前属于LVS从版图里面提取不到器件，你可以测试一下，新建一个layout，将版图这两个器件单独放入里面跑L ...

可以帮忙看看规则文件应该怎么设置吗

Cheney聪 · 发表于 2024-5-31 14:11:54

把加的那个删掉

MISU · 发表于 2024-5-31 14:16:37

Cheney聪发表于 2024-5-31 14:11
把加的那个删掉

#DEFINE MIM_PROPERTY C
#DEFINE RES_PROPERTY R

顶头的这两句需要删吗，另外其他的哪里需要修改吗

Cheney聪 · 发表于 2024-5-31 14:17:18

你删掉跑一下，看结果

MISU · 发表于 2024-5-31 14:20:49

Cheney聪发表于 2024-5-31 14:17
你删掉跑一下，看结果

还是一样的电容电阻** missing instance ** 以及中间的那根线** missing net **

fzj1992130 · 发表于 2024-5-31 14:28:57

PDK按照要求正常安装吗？是否选择了正确的电阻？

test2022 · 发表于 2024-5-31 14:29:54

赞同楼上，report 贴出看下

MISU · 发表于 2024-5-31 14:33:31

test2022 发表于 2024-5-31 14:29
赞同楼上，report 贴出看下

你好  这是report文件

               ##################################################
               ##                                           ##
               ##       C A L I B R E S Y S T E M       ##
               ##                                           ##
               ##          L V S R E P O R T             ##
               ##                                           ##
               ##################################################

REPORT FILE NAME:       OP_2stage_mul.lvs.report
LAYOUT NAME:             /home/work/learn_lib/LVS/OP_2stage_mul.sp ('OP_2stage_mul')
SOURCE NAME:             /home/work/learn_lib/LVS/OP_2stage_mul.src.net ('OP_2stage_mul')
RULE FILE:             /home/work/learn_lib/LVS/_SmicSP12R_cal018_epm_sali_p2mtx_18335155.lvs_
CREATION TIME:          Fri May 31 14:19:43 2024
CURRENT DIRECTORY:       /home/work/learn_lib/LVS
USER NAME:             work
CALIBRE VERSION:       v2015.2_36.27 Wed Jul 1 10:06:07 PDT 2015

                           OVERALL COMPARISON RESULTS

               # #       #####################
               # #       #                #
                  #          #    INCORRECT    #
               # #       #                #
               # #       #####################

  Error: Different numbers of nets.
  Error: Different numbers of instances.
  Warning:  Unbalanced smashed mosfets were matched.

**************************************************************************************************************
                                    CELL  SUMMARY
**************************************************************************************************************

  Result       Layout                      Source
  ----------- -----------                --------------
  INCORRECT    OP_2stage_mul                OP_2stage_mul

**************************************************************************************************************
                                    LVS PARAMETERS
**************************************************************************************************************

o LVS Setup:

// LVS COMPONENT TYPE PROPERTY
// LVS COMPONENT SUBTYPE PROPERTY
// LVS PIN NAME PROPERTY
LVS POWER NAME                      "VDD"
LVS GROUND NAME                      "GND"
LVS CELL SUPPLY                      NO
LVS RECOGNIZE GATES                   ALL
LVS IGNORE PORTS                      NO
LVS CHECK PORT NAMES                YES
LVS IGNORE TRIVIAL NAMED PORTS       NO
LVS BUILTIN DEVICE PIN SWAP          YES
LVS ALL CAPACITOR PINS SWAPPABLE    YES
LVS DISCARD PINS BY DEVICE          NO
LVS SOFT SUBSTRATE PINS             NO
LVS INJECT LOGIC                      YES
LVS EXPAND UNBALANCED CELLS          YES
LVS FLATTEN INSIDE CELL             NO
LVS EXPAND SEED PROMOTIONS          NO
LVS PRESERVE PARAMETERIZED CELLS    NO
LVS GLOBALS ARE PORTS                YES
LVS REVERSE WL                      NO
LVS SPICE PREFER PINS                YES
LVS SPICE SLASH IS SPACE             YES
LVS SPICE ALLOW FLOATING PINS       YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS    NO
LVS SPICE CONDITIONAL LDD             NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
LVS SPICE IMPLIED MOS AREA          NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS          NO
LVS SPICE REDEFINE PARAM             NO
LVS SPICE REPLICATE DEVICES          NO
LVS SPICE SCALE X PARAMETERS          NO
LVS SPICE STRICT WL                   NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES                   NO
LVS EXACT SUBTYPES                   NO
LAYOUT CASE                         NO
SOURCE CASE                         NO
LVS COMPARE CASE                      NO
LVS DOWNCASE DEVICE                   NO
LVS REPORT MAXIMUM                   50
LVS PROPERTY RESOLUTION MAXIMUM       65536
// LVS SIGNATURE MAXIMUM
// LVS FILTER UNUSED OPTION
// LVS REPORT OPTION
LVS REPORT UNITS                      YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// LVS IGNORE DEVICE PIN

// Reduction

LVS REDUCE SERIES MOS                NO
LVS REDUCE PARALLEL MOS             YES
LVS REDUCE SEMI SERIES MOS          NO
LVS REDUCE SPLIT GATES                YES
LVS REDUCE PARALLEL BIPOLAR          YES
LVS REDUCE SERIES CAPACITORS          YES
LVS REDUCE PARALLEL CAPACITORS       YES
LVS REDUCE SERIES RESISTORS          YES
LVS REDUCE PARALLEL RESISTORS       YES
LVS REDUCE PARALLEL DIODES          YES
LVS REDUCTION PRIORITY                PARALLEL

LVS SHORT EQUIVALENT NODES          NO

// Trace Property

TRACE PROPERTY  mn(n18e2r)  l l 5
TRACE PROPERTY  mn(n18e2r)  w w 5
TRACE PROPERTY  mn(nz18e2r)  l l 5
TRACE PROPERTY  mn(nz18e2r)  w w 5
TRACE PROPERTY  mp(p18e2r)  l l 5
TRACE PROPERTY  mp(p18e2r)  w w 5
TRACE PROPERTY  mn(n33e2r)  l l 5
TRACE PROPERTY  mn(n33e2r)  w w 5
TRACE PROPERTY  mp(p33e2r)  l l 5
TRACE PROPERTY  mp(p33e2r)  w w 5
TRACE PROPERTY  mn(n50e2r)  l l 5
TRACE PROPERTY  mn(n50e2r)  w w 5
TRACE PROPERTY  mp(p50e2r)  l l 5
TRACE PROPERTY  mp(p50e2r)  w w 5
TRACE PROPERTY  mn(nz50e2r)  l l 5
TRACE PROPERTY  mn(nz50e2r)  w w 5
TRACE PROPERTY  mn(n155e2r)  l l 5
TRACE PROPERTY  mn(n155e2r)  w w 5
TRACE PROPERTY  mn(nz155e2r)  l l 5
TRACE PROPERTY  mn(nz155e2r)  w w 5
TRACE PROPERTY  mp(p155e2r)  l l 5
TRACE PROPERTY  mp(p155e2r)  w w 5
TRACE PROPERTY  mn(n18d)  l l 5
TRACE PROPERTY  mn(n18d)  w w 5
TRACE PROPERTY  mn(n18h)  l l 5
TRACE PROPERTY  mn(n18h)  w w 5
TRACE PROPERTY  mn(nsg)  l l 5
TRACE PROPERTY  mn(nsg)  w w 5
TRACE PROPERTY  mn(ncg)  l l 5
TRACE PROPERTY  mn(ncg)  w w 5
TRACE PROPERTY  pvar18e2r_ckt  wr wr 5
TRACE PROPERTY  pvar18e2r_ckt  lr lr 5
TRACE PROPERTY  pvar18e2r_ckt  nf nf 0
TRACE PROPERTY  q(pnp18a4e2r)  a a 5
TRACE PROPERTY  q(pnp18a25e2r)  a a 5
TRACE PROPERTY  q(pnp18a100e2r)  a a 5
TRACE PROPERTY  q(pnp33a4e2r)  a a 5
TRACE PROPERTY  q(pnp33a25e2r)  a a 5
TRACE PROPERTY  q(pnp33a100e2r)  a a 5
TRACE PROPERTY  d(pdio18e2r)  a a 5
TRACE PROPERTY  d(pdio33e2r)  a a 5
TRACE PROPERTY  d(pdio50e2r)  a a 5
TRACE PROPERTY  d(pdio155e2r)  a a 5
TRACE PROPERTY  d(ndio18e2r)  a a 5
TRACE PROPERTY  d(ndio33e2r)  a a 5
TRACE PROPERTY  d(ndio50e2r)  a a 5
TRACE PROPERTY  d(ndio155e2r)  a a 5
TRACE PROPERTY  d(nzdio50e2r)  a a 5
TRACE PROPERTY  d(nzdio155e2r)  a a 5
TRACE PROPERTY  d(nwdioe2r)  a a 5
TRACE PROPERTY  d(dnwdioe2r)  a a 5
TRACE PROPERTY  c(cgttow)  c c 5
TRACE PROPERTY  pipe2r_ckt  c c 5
TRACE PROPERTY  r(rpgt)  r r 5
TRACE PROPERTY  r(rngtsab)  r r 5
TRACE PROPERTY  r(rpgtsab)  r r 5
TRACE PROPERTY  r(rncgsab)  r r 5
TRACE PROPERTY  r(rm1)  r r 5
TRACE PROPERTY  r(rm2)  r r 5
TRACE PROPERTY  r(rm3)  r r 5
TRACE PROPERTY  r(rm4)  r r 5
TRACE PROPERTY  r(rm5)  r r 5
TRACE PROPERTY  r(rm6)  r r 5

               CELL COMPARISON RESULTS ( TOP LEVEL )

               # #       #####################
               # #       #                #
                  #          #    INCORRECT    #
               # #       #                #
               # #       #####################

  Error: Different numbers of nets (see below).
  Error: Different numbers of instances (see below).
  Warning:  Unbalanced smashed mosfets were matched.

LAYOUT CELL NAME:       OP_2stage_mul
SOURCE CELL NAME:       OP_2stage_mul

--------------------------------------------------------------------------------------------------------------

INITIAL NUMBERS OF OBJECTS
--------------------------

            Layout Source       Component Type
            ------ ------       --------------
Ports:             6       6

Nets:             12       13 *

Instances:       26       7 * MN (4 pins)
                  49       7 * MP (4 pins)
                  0       1 * C (2 pins)
                  0       1 * R (2 pins)
            ------ ------
Total Inst:       75       16

NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------

            Layout Source       Component Type
            ------ ------       --------------
Ports:             6       6

Nets:             11       12 *

Instances:       5       5       MN (4 pins)
                  6       6       MP (4 pins)
                  0       1 * C (2 pins)
                  0       1 * R (2 pins)
                  1       1       _smn2v (4 pins)
            ------ ------
Total Inst:       12       14

   * = Number of objects in layout different from number in source.

**************************************************************************************************************
                              INCORRECT OBJECTS
**************************************************************************************************************

LEGEND:
-------

  ne  = Naming Error (same layout name found in source
      circuit, but object was matched otherwise).

**************************************************************************************************************
                                 INCORRECT NETS

DISC#  LAYOUT NAME                                              SOURCE NAME
**************************************************************************************************************

  1 ** missing net **                                        net26

**************************************************************************************************************
                              INCORRECT INSTANCES

DISC#  LAYOUT NAME                                              SOURCE NAME
**************************************************************************************************************

  2 ** missing instance **                                  RR0  R(RNDIF)

--------------------------------------------------------------------------------------------------------------

  3 ** missing instance **                                  CC2  C(MIME2R)

**************************************************************************************************************
                           INFORMATION AND WARNINGS
**************************************************************************************************************

               Matched Matched Unmatched Unmatched Component
               Layout    Source    Layout    Source Type
               ------- ------- --------- --------- ---------
Ports:             6       6          0          0

Nets:             11       11          0          1

Instances:          5       5          0          0 MN(N33E2R)
                     6       6          0          0 MP(P33E2R)
                     0       0          0          1 C(MIME2R)
                     0       0          0          1 R(RNDIF)
                     1       1          0          0 _smn2v
               ------- ------- --------- ---------
Total Inst:       12       12          0          2

o Statistics:

68 layout mos transistors were reduced to 6.
   62 mos transistors were deleted by parallel reduction.
2 source mos transistors were reduced to 1.
   1 mos transistor was deleted by parallel reduction.

o Initial Correspondence Points:

Ports:       VDD GND VIN- VIN+ OUT BIS

o Matched Mosfets Which Have Been Unequally Reduced:

   M1(21.585,26.480)                                        MM14
   M12(40.225,40.395)                                     MM15
   M11(40.225,26.480)                                     ** missing smashed mosfet **
   M2(21.585,40.395)                                        ** missing smashed mosfet **

**************************************************************************************************************
                                       SUMMARY
**************************************************************************************************************

Total CPU Time:    0 sec
Total Elapsed Time:  0 sec

MISU · 发表于 2024-5-31 14:34:19

fzj1992130 发表于 2024-5-31 14:28
PDK按照要求正常安装吗？是否选择了正确的电阻？

是正常安装的，电阻选的是rndif

test2022 · 发表于 2024-5-31 14:36:32

电阻、电容都没识别出来，看下安装PDK选项是不是选对了

[求助] LVS仿真电容电阻始终过不了

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