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我编了一个程序,只能进行功能级仿真,以下的仿真都进行不了,为什么?程序如下:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity b_clk is
Port (
clk ,reset : in std_logic;
write: in std_logic ;
data :in std_logic_vector ( 0 to 7 );
tx : out std_logic
);
end b_clk;
architecture Behavioral of b_clk is
signal txclk , txdone ,txdata_ready ,txparity ,txtag1 ,txtag2 ,parity : std_logic ;
signal txreg ,txhold : std_logic_vector ( 0 to 7 ) ;
begin
p1 :process ( clk , reset )
variable txcnt :std_logic_vector ( 0 to 2 ) ;
begin
if reset = '1' then --产生一个时钟
txclk <= '0' ;
txcnt := "000";
elsif clk = '1' AND clk'event then
if txcnt = "000" then
txclk <= not txclk ;
end if ;
txcnt := txcnt + "001";
end if ;
end process ;
p2 : process ( reset ,txclk ) --串并转换并奇偶校验
begin
if reset = '1'then
txreg <= ( others => '0' );
txparity <= '0' ;
tx <= '0';
elsif txclk = '1' and txclk'event then
if ( txdone and txdata_ready ) = '1' then
txreg <= txhold ;
txparity <= '1' ;
txtag1 <= '1' ;
txtag2 <= '1' ;
tx<= '0' ;
else
txreg <= txreg ( 1 to 7 ) & txtag1 ;
txtag1 <= txtag2;
txtag2 <= '0' ;
txparity <= txparity xor txreg ( 0 ) ;
if txdone = '1' then
tx <= '1' ;
elsif parity = '1' then
tx <= txparity ;
else
tx <= txreg ( 0 ) ;
end if ;
end if ;
end if ;
end process ;
txdone <= not ( txreg ( 0 ) or txreg ( 1 ) or txreg ( 2 ) or txreg ( 3 ) or txreg ( 4 ) or
txreg ( 5 ) or txreg ( 6 ) or txreg ( 7 ) or txtag1 or txtag2 ) ;
parity <=txreg( 1 ) and not ( txreg ( 2 ) or txreg ( 3 ) or txreg ( 4 ) or txreg (5) or txreg( 6 ) or txreg ( 7 ) or txtag1 or txtag2 ) ;
p3 : process ( reset , clk )
variable txdone1, wr1 ,wr2 :std_logic ;
begin
if reset = '1' then
wr1 := '0' ;
wr2 := '0' ;
txdata_ready <='0';
elsif clk'event and clk = '1' then
if wr1 = '0' and wr2 = '1' then
txdata_ready <= '1' ;
elsif txdone = '0' and txdone1 = '1' then
txdata_ready <= '0' ;
end if ;
wr2 := wr1 ;
wr1 := write ;
txdone1 := txdone ;
end if ;
end process;
txhold <= data when write = '1' else txhold ;
end Behavioral;
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