Prime Time User Guide 中英对照 第四章

LunarJanuary

Before you perform timing analysis, you need to read and link the design and associated logic libraries. To learn about working with design data, see these topics:

在执行时序分析之前，您需要阅读并link设计和相关逻辑库。若要了解如何使用设计数据，请参阅以下主题：

• Logic Libraries

• Reading and Linking the Design

• Working With Design Objects

• Setting the Current Design and Current Instance

• Working With Attributes

• Saving Attributes

Logic Libraries

A logic library describes the timing and function of macro cells in an ASIC technology by using the Library Compiler tool. Other Synopsys tools, such as the Design Compiler synthesis tool and the IC Compiler place-and-route tool, also use these logic libraries.

逻辑库通过使用库编译器工具描述了 ASIC 技术中macro cells的时序和功能。其他 Synopsys 工具（如 Design Compiler 综合工具和 IC Compiler 布局布线工具）也使用这些逻辑库。

A logic library contains library cell descriptions that include

逻辑库包含库cell描述，包括

• Cell, bus, and pin structure that describes each cell’s connection to the outside world

• cell、总线和描述每个单元与外界连接的pin结构

• Logic function of output pins of cells

• cell输出pin的逻辑功能

• Timing analysis and design optimization information, such as the pin-to-pin timing relationships, delay parameters, and timing constraints for sequential cells

• 时序分析和设计优化信息，例如时序cells的pin之间的时序关系、延迟参数和时序约束

• Other parameters that describe area, power, and design rule constraints

• 描述面积、功耗和设计规则约束的其他参数

PrimeTime can read logic libraries in the .db and .lib formats. The libraries can have different units of time, capacitance, and voltage.

PrimeTime可以读取.db和.lib格式的逻辑库。这些库可以具有不同的时序、电容和电压单位。

For more information about logic libraries, see the Library Compiler documentation.

有关逻辑库的详细信息，请参阅库编译器文档。

Reading and Linking the Design

Before you perform timing analysis, you need to read and link the design and logic libraries. PrimeTime can read the following file formats:

在执行时序分析之前，您需要读取并link设计和逻辑库文件。PrimeTime可以读取以下文件格式：

To read and link the design data, follow these steps:

• Specify the directories in which PrimeTime searches for designs, logic libraries, and other design data such as timing models. To do this, set the search_path variable. For example:
• 指定PrimeTime搜索设计、逻辑库和其他设计数据（如时序模型）的目录。为此，请设置 search_path 变量。例如：
  pt_shell> set_app_var search_path ". /abc/design /abc/libs"
  PrimeTime searches the directories in the order that you specify.
• Specify the libraries in which PrimeTime finds elements in the design hierarchy by setting the link_path variable. For example:
  2. 通过设置 link_path 变量来指定 PrimeTime 查找design hierarchy的库元素。例如：
  pt_shell> set_app_var link_path "* STDLIB.db"
  The variable can contain an asterisk (*), library names, and file names. The asterisk instructs PrimeTime to search for a design in memory. PrimeTime searches libraries in the order that you specify. The main library is the first library in the link path.
  该变量可以包含星号 （*）、库名称和文件名。星号指示PrimeTime在内存中搜索design。PrimeTime按您指定的顺序搜索库。链接路径中的第一个库为主库。
• Read the design into memory:
  pt_shell> read_verilog TOP.v
  If the search path includes files that contain the subdesigns, you need to read only the top-level design. The search path entry must include the full path to the subdesign file, not just the directory containing the file.
  如果搜索路径下有包含subdesign的文件，则只需读取顶层设计。搜索路径条目必须包含subdesign文件的完整路径，而不仅仅是包含该文件的目录。
• Link the design to resolve references to library cells and subdesigns:
  pt_shell> link_design TOP
  During design linking, the tool automatically loads the subdesigns if the subdesign names match the file names.
• Verify the loaded designs and libraries by using the list_designs and list_libs commands.
  

5. 使用 list_designs 和 list_libs 命令验证加载的设计和库。

Working With Design Objects

Designs are hierarchical entities composed of objects such as cells, ports, and nets.

In the PrimeTime tool, a design contains the objects in the following table.

To constrain the design, perform detailed timing analysis, and locate the source of timing problems, you need to access the design objects. You can do this by creating collections of objects with the appropriate “get” command. For example, the get_ports command creates a collection of ports.

要约束design、执行详细的时序分析并定位时序问题的根源，您需要访问设计对象。您可以通过使用合适的“get”命令创建对象的集合来做到。例如，get_ports 命令创建port的集合。

You can nest the result of a “get” command within another command that operates on the objects. For example:

您可以将“get”命令的结果嵌套在对对象进行操作的另一个命令中。例如：

pt_shell> set_input_delay 2.3 [get_ports IN*]

See Also

• “Searching for Design Objects” in Using Tcl With Synopsys Tools

Setting the Current Design and Current Instance

The current design and current instance define the focus of many PrimeTime commands. To set or return the current design or instance, use the following commands.

Working With Attributes

An attribute is a string or value associated with an object that carries some information about that object. You can write programs in Tcl to get attribute information from the design database and generate custom reports on the design.

属性是与对象关联的字符串或值，它携带有关该对象的一些信息。您可以在 Tcl 中编写程序，从design数据库中获取属性信息，并生成有关设计的自定义报告。

PrimeTime provides the following commands for setting, reporting, listing, and creating attributes.

For descriptions of the predefined application attributes of each object class, see the man pages. For example, to see the descriptions of library cell attributes, use the following command:

pt_shell> man lib_cell_attributes

Saving Attributes

The save_session command does not save attributes. To save attributes that you applied during a session, create a script in the in the pt_shell, dc_shell, or dctcl format by using the write_script command. When you restore the PrimeTime session, you can use the script to re-create the attributes on the design.

save_session 命令不保存属性。若要保存在会话期间应用的属性，请使用 write_script 命令以 pt_shell、dc_shell 或 dctcl 格式创建脚本。恢复PrimeTime session时，可以使用脚本在design上重新创建属性。