ISSCC2024 Paper 分session

孤岛巨象

Session 1 Overview: Plenary       
        1.1: Semiconductor Industry: Present & Future       
        1.2: Racing Down the Slopes of Moore’s Law       
        1.3: Computing in the Era of Generative AI       
        1.4: Fueling Semiconductor Innovation and Entrepreneurship in the Next Decade       
Session 2 Overview: Processors and Communication SoCs       
        2.1: A 4nm 3.4GHz Tri-Gear Fully Out-of-Order ARMv9.2 CPU Subsystem-Based 5G Mobile SoC       
        2.2: “Zen 4c”: The AMD 5nm Area-Optimized x86-64 Microprocessor Core       
        2.3: Emerald Rapids: 5th-Generation Intel® Xeon® Scalable Processors       
        2.4: ATOMUS: A 5nm 32TFLOPS/128TOPS ML System-on-Chip for Latency Critical Applications       
        2.5: A 28nm Physical-Based Ray-Tracing Rendering Processor for Photorealistic Augmented Reality with Inverse Rendering and Background Clustering for Mobile Devices       
        2.6: A 131mW 6.4Gbps 256×32 Multi-User MIMO OTFS Detector for Next-Gen Communication Systems       
        2.7: BayesBB: A 9.6Gbps 1.61ms Configurable All-Message-Passing Baseband-Accelerator for B5G/6G Cell-Free Massive-MIMO in 40nm CMOS       
        2.8: A 21.9ns 15.7Gbps/mm2 (128, 15) BOSS FEC Decoder for 5G/6G URLLC Applications       
Session 3 Overview: Analog Techniques       
        3.1: A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/°C from -20°C to 125°C       
        3.2: A 0.028mm2 32MHz RC Frequency Reference in 0.18μm CMOS with ±900ppm Inaccuracy from -40°C to 125°C and ±1600ppm Inaccuracy After Accelerated Aging       
        3.3: A 0.5V 6.14μW Trimming-Free Single-XO Dual-Output Frequency Reference with [5.1nJ, 120μs] XO Startup and [8.1nJ, 200μs] Successive-Approximation-Based RTC Calibration       
        3.4: A 14b 98Hz-to-5.9kHz 1.7-to-50.8μW BW/Power Scalable Sensor Interface with a Dynamic Bandgap Reference and an Untrimmed Gain Error of ±0.26% from -40°C to 125°C       
        3.5: A 4mW 45pT/√Hz Magnetoimpedance-Based ΔΣ Magnetometer with Background Gain Calibration and Short-Time CDS Techniques       
        3.6: An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing       
        3.7: A β-Compensated NPN-Based Temperature Sensor with ±0.1°C (3σ) Inaccuracy from -55°C to 125°C and a 200fJ∙K2 Resolution FoM       
        3.8: A 0.65V 900μm2 BEoL RC-Based Temperature Sensor with ±1°C Inaccuracy from -25°C to 125°C       
        3.9: A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in 12-bit SAR ADC Using 3nm GAA’s 0.7V Thin-Gate-Oxide Transistor       
        3.10: A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS       
Session 4 Overview: High Performance Transceivers and Transmitters for Communication and Ranging       
        4.1: A 79.7μW Two-Transceiver Direct-RF 7.875GHz UWB RadarSoC in 40nm CMOS       
        4.2: A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving -46dB TX/RX EVM Floor at 7.1GHz for a 4K-QAM 320MHz Signal       
        4.3: A 43mm2 Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 4×4 MIMO with 1K-QAM       
        4.4: A Highly-Integrated 6-Phase Cell-Reused Digital Transmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection       
        4.5: A Reconfigurable, Multi-Channel Quantized-Analog Transmitter with <-35dB EVM and <-51dBc ACLR in 22nm FDSOI       
Session 5 Overview: Wireless RF and mm-Wave Receiver Techniques       
        5.1: A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression       
        5.2: 0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving +14/+16.5dBm 3rd/5th IB Harmonic B1dB       
        5.3: A 0.072mm2 18-to-21GHz Non-Uniform Sub-Sampling Receiver with a Non-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection in 28nm CMOS       
        5.4: A 22.4-to-30.7GHz Phased-Array Receiver with Beam-Pattern Null-Steering and Beam-Tracking Techniques Achieving >30.2dB OTA-Tested Spatial Rejection       
        5.5: A Stacking Mixer-First Receiver Achieving >20dBm Adjacent-Channel IIP3 Consuming less than 25mW       
Session 6 Overview: Imagers and Ultrasound       
        6.1: 12Mb/s 4×4 Ultrasound MIMO Relay with Wireless Power and Communication for Neural Interfaces       
        6.2: An Ultrasound-Powering TX with a Global Charge-Redistribution Adiabatic Drive Achieving 69% Power Reduction and 53° Maximum Beam Steering Angle for Implantable Applications       
        6.3: Imager with In-Sensor Event Detection and Morphological Transformations with 2.9pJ/pixel×frame Object Segmentation FOM for Always-On Surveillance in 40nm       
        6.4: A Resonant High-Voltage Pulser for Battery-Powered Ultrasound Devices       
        6.5: A 0.5°-Resolution Hybrid Dual-Band Ultrasound Imaging SoC for UAV Applications       
        6.6: Withdrawn by ISSCC       
        6.7: A 160×120 Flash LiDAR Sensor with Fully Analog-Assisted In-Pixel Histogramming TDC Based on Self-Referenced SAR ADC       
        6.8: A 256×192-Pixel 30fps Automotive Direct Time-of-Flight LiDAR Using 8× Current-Integrating-Based TIA, Hybrid Pulse Position/Width Converter, and Intensity/CNN-Guided 3D Inpainting       
        6.9: A 0.35V 0.367TOPS/W Image Sensor with 3-Layer Optical-Electronic Hybrid Convolutional Neural Network       
        6.10: A 1/1.56-inch 50Mpixel CMOS Image Sensor with 0.5μm pitch Quad Photodiode Separated by Front Deep Trench Isolation       
        6.11: A 320x240 CMOS LiDAR Sensor with 6-Transistor nMOS-Only SPAD Analog Front-End and Area-Efficient Priority Histogram Memory       
Session 7 Overview: Ultra-High Speed Wireline       
        7.1: A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET       
        7.2: A 224Gb/s sub pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET       
        7.3: A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS       
        7.4: A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and −74.2dBc Reference Spur       
        7.5: A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE       
        7.6: A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS       
        7.7: A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS       
        7.8: A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs Under 50mV Supply Noise       
        7.9: An 8b 6-12GHz 0.18mW/GHz DC Modulated Ramp-Based Phase Interpolator in 65nm CMOS Process       
Session 8 Overview: Hybrid DC-DC Converters       
        8.1: A 94.5%-Peak-Efficiency 3.99W/mm2-Power-Density Single-Inductor Bipolar-Output Converter with a Concise PWM Control for AMOLED Displays       
        8.2: A 96.9%-Peak-Efficiency Bilaterally-Symmetrical Hybrid Buck-Boost Converter Featuring Seamless Single-Mode Operation, Always-Reduced Inductor Current, and the Use of All CMOS Switches       
        8.3: A Li-ion-Battery-Input 1-to-6V-Output Bootstrap-Free Hybrid Buck-or-Boost Converter Without RHP Zero Achieving 97.3% Peak Efficiency 6μs Recovery Time and 1.13μs/V DVS Rate       
        8.4: A Fast-Transient 3-Fine-Level Buck-Boost Hybrid DC-DC Converter with Half-Voltage-Stress on All Switches and 98.2% Peak Efficiency       
        8.5: A 6nA Fully-Autonomous Triple-Input Hybrid-Inductor-Capacitor Multi-Output Power Management System with Multi-Rail Energy Sharing, All-Rail Cold Startup, and Adaptive Conversion Control for mm-scale Distributed Systems       
        8.6: An Integrated Dual-side Series/Parallel Piezoelectric Resonator-based 20-to-2.2V DC-DC Converter Achieving a 310% Loss Reduction       
        8.7: A 92.7% Peak Efficiency 12V-to-60V Input to 1.2V Output Hybrid DC-DC Converter Based on a Series-Parallel-Connected Switched Capacitor       
        8.8: A 97.18% Peak-Efficiency Asymmetrically Implemented Dual-phase (AID) Converter with a full Voltage-Conversion Ratio (VCR) between 0-and-1       
        8.9: A 96.5% Peak Efficiency Duty-Independent DC-DC Step-Up Converter with Low Input-Level Voltage Stress and Mode-Adaptive Inductor Current Reduction       
        8.10: A 5V-to-150V Input-Parallel Output-Series Hybrid DC-DC Boost Converter Achieving 76.4mW/mg Power Density and 80% Peak Efficiency       
        8.11: A 48V-to-5V Buck Converter with Triple EMI Suppression Circuit Meeting CISPR 25 Automotive Standards       
Session 9 Overview: Noise-Shaping and SAR ADCs       
        9.1: A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting       
        9.2: A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm       
        9.3: A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integrating Amplifier Achieving 173dB FoMs       
        9.4: A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique       
        9.5: A 118.5dBA DR 3.3mW Audio ADC with a Class-B Resistor DAC, Non-Overlap DEM and Continuous-Time Quantizer       
        9.6: A 6th-Order Quadrature CTDSM using Double-OTA and Quadrature NSSAR with 171.3dB FoMs in 14nm       
        9.7: A 94.3dB SNDR 184dB FoMs 4th-Order Noise-Shaping SAR ADC with Dynamic-Amplifier-Assisted Cascaded Integrator       
        9.8: A 9.3nV/rtHz 20b 40MS/s 94.2dB DR Signal-Chain Friendly Precision SAR Converter       
        9.9: A 2.72fJ/conv 13b 2MS/s SAR ADC Using Dynamic Capacitive Comparator with Wide Input Common Mode       
Session 10 Overview: Frequency Synthesis       
        10.1: An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM       
        10.2: A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm       
        10.3: A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spurand 143.7fs Integrated Jitter       
        10.4: A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and Wandering Spurs       
        10.5: A 76fsrms-Jitter and −65dBc-Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique       
        10.6: A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion       
        10.7: An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051% rms Frequency Error under a 2.3GHz Chirp Bandwidth, 2.3GHz/μs Slope, and 50ns Idle Time in 65nm CMOS       
        10.8: A 281GHz, −1.5dBm Output-Power CMOS Signal Source Adopting a 46fsrms Jitter D-Band Cascaded Subharmonically Injection-Locked Sub-Sampling PLL with a 274MHz Reference       
        10.9: A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, −253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment       
Session 11 Overview: Highlighted Chip Releases: Digital and Machine Learning Processors       
        11.1:  AMD InstinctTM MI300 Series Modular Chiplet Package – HPC and AI Accelerator for Exa-Class Systems       
        11.2: A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint       
        11.3: Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge       
        11.4: IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip       
Session 12 Overview: Electromagnetic Interface ICs for Information and Power Transfer       
        12.1: Monolithically Integrated Sub-63 fJ/b 8-Channel 256Gb/s Optical Transmitter with Autonomous Wavelength Locking in 45nm CMOS SOI       
        12.2: A mm-Wave/Sub-THz Synthesizer-Free Coherent Receiver with Phase Reconstruction Through Mixed-Signal Kramer-Kronig Processing       
        12.3: A Scalable and Instantaneously Wideband 5GS/s RF Correlator Based on Charge Thresholding Achieving 8-bit ENOB and 152 TOPS/W Compute Efficiency       
        12.4: A 19μW 200Mb/s IoT Tag Demonstrating High-Definition Video Streaming via a Digital-Switch-Based Reconfigurable 16-QAM Backscatter Communication Technique       
        12.5: A Packageless Anti-Tampering Tag Utilizing Unclonable Sub-THz Wave Scattering at the Chip-Item Interface       
        12.6: A 64.4% Efficiency 5.8GHz RF Wireless Power Transfer Receiver with GaAs E-pHEMT Rectifier and 45.2μs MPPT Time SIDITO Buck-Boost Converter Using VOC Prediction Scheme       
Session 13 Overview: High-Density Memories and High-Speed Interfaces       
        13.1: A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry       
        13.2: A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process       
        13.3: A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate       
        13.4: A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization       
        13.5: A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis Capacitive-Peaking Crosstalk-Cancellation Scheme for Memory Interfaces in 28nm CMOS       
        13.6: A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration       
        13.7: A 1Tb Density 3b/Cell 3D-NAND Flash on a 2YY-Tier Technology with a 300MB/s Write Throughput       
        13.8: A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction       
        13.9: A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency       
        13.10: A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets       
Session 14 Overview: Digital Techniques for System Adaptation, Power Management and Clocking       
        14.1: A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC       
        14.2: Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS       
        14.3: A 3nm Adaptive Clock Duty-Cycle Controller for Mitigating Aging-Induced Clock Duty-Cycle Distortion       
        14.4: A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU       
        14.5: A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration       
        14.6: A 10A Computational Digital LDO Achieving 263A/mm2 Current Density with Distributed Power-Gating Switches and Time-Based Fast-Transient Controller for Mobile SoC Application in 3nm GAAFET       
        14.7: A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS       
        14.8:  KASP: A 96.8% 10-Keyword Accuracy and 1.68μJ/Classification Keyword Spotting and Speaker Verification Processor Using Adaptive Beamforming and Progressive Wake-Up       
        14.9: A Monolithic 10.5W/mm2 600MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16nm-Class CMOS       
        14.10: 34.7A/mm2 Scalable Distributed All-Digital 6×6 Dot-LDOs Featuring Freely Linkable Current-Sharing Network: A Fine-Grained On-Chip Power Delivery Solution in 28nm CMOS       
Session 15 Overview: Embedded Memories & Ising Computing       
        15.1: A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch       
        15.2: A 2048×60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia       
        15.3: A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture       
        15.4: Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node       
        15.5: LISA: A 576×4 All-in-One Replica-Spins Continuous-Time Latch-Based Ising Computer Using Massively-Parallel Random-Number Generations and Replica Equalizations       
        15.6: e-Chimera: A Scalable SRAM-Based Ising Macro with Enhanced-Chimera Topology for Solving Combinatorial Optimization Problems Within Memory       
        15.7: A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249μm2 Bit-Cell, a 3.2GB/S Read Throughput, a 10KCycle Write Endurance and a 10-Year Retention at 105°C       
        15.8: A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs       
        15.9: A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes       
Session 16 Overview: Security: From Processors to Circuits       
        16.1: A 2.7-to-13.3μJ/boot/slot Flexible RNS-CKKS Processor in 28nm CMOS Technology for FHE-Based Privacy-Preserving Computing       
        16.2: A 28nm 69.4kOPS 4.4μJ/Op Versatile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems       
        16.3: 3nm Physical Unclonable Function with Multi-Mode Self-Destruction and 3.48×10-5 Bit Error Rate       
        16.4: High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking       
        16.5: A Synthesizable Design-Agnostic Timing Fault Injection Monitor Covering 2MHz to 1.26GHz Clocks in 65nm CMOS       
        16.6: PACTOR: A Variation-Tolerant Probing-Attack Detector for a 2.5Gb/s×4-Channel Chip-to-Chip Interface in 28nm CMOS       
        16.7: Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits       
        16.8: A 60Mb/s TRNG with PVT-Variation-Tolerant Design Based on STR in 4nm       
Session 17 Overview: Emerging Sensing and Computing Technologies       
        17.1: Omnidirectional Magnetoelectric Power Transfer for Miniaturized Biomedical Implants via Active Echo       
        17.2: A Miniature Multi-Nuclei NMR/MRI Platform with a High-Voltage SOI ASIC Achieving a 134.4dB Image SNR with a 173×250×103μm3 Resolution       
        17.3: A Fully Wireless, Miniaturized, Multicolor Fluorescence Image Sensor Implant for Real-Time Monitoring in Cancer Therapy       
        17.4: Environmentally-Friendly Disposable Circuit and Battery System for Reducing Impact of E-Wastes       
        17.5: A 24V Mini-Coil Magnetic Neural Stimulator with Closed-Loop Deadtime Control and ZCS Control Achieving 99.76% Charge Recovery Efficiency       
        17.6: Fully Integrated CMOS Ferrofluidic Biomolecular Processing Platform with On-Chip Droplet-Based Manipulation, Multiplexing and Sensing       
        17.7: Droplet Microfluidics Co-Designed with Real-Time CMOS Luminescence Sensing and Impedance Spectroscopy of 4nL Droplets at a 67mm/s Velocity       
        17.8: 0.4V 988nW Time-Domain Audio Feature Extraction for Keyword Spotting Using Injection-Locked Oscillators       
        17.9: A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-Domain Computing and Scalable 5T-SRAM       
        17.10: A 0.4V, 750nW, Individually Accessible Wireless Capacitive Sensor Interface IC for a Tactile Sensing Network       
        17.11: A 9mW Ultrasonic Through Transmission Transceiver for Non-Invasive Intracranial Pressure Sensing       
Session 18 Overview: High-Performance Optical Transceivers       
        18.1: A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS       
        18.2: A 4×64Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter       
        18.3: An 8b 160GS/s 57GHz Bandwidth Time-Interleaved DAC and Driver-Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm       
        18.4: A 200GS/s 8b 20fJ/c-s Receiver with >60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET       
Session 19 Overview: RF to mm-Wave Oscillators and Multipliers       
        19.1: A 7.5GHz Subharmonic Injection-Locked Clock Multiplier with a 62.5MHz Reference, -259.7dB FoMJ, and -56.6dBc ReferenceSpur       
        19.2: A 12.4% Efficiency, 11dBm Psat, Odd-Harmonics-Recycling, 62-to-92GHz CMOS Frequency Quadrupler Using an Amplitude-Phase Coordinating Technique       
        19.3: An 8.9-to-21.9GHz Single-Core Oscillator with Reconfigurable Class-F-1 and Enhanced-Colpitts Dual-Mode Operation Achieving 209dBc/Hz FoMT       
        19.4: A 0.07mm2 20-to-23.8GHz 8-phase Oscillator IncorporatingMagnetic + Dual-Injection Coupling Achieving 189.2dBc/HzFoM@10MHz and 200.7dBc/Hz FoMA in 65nm CMOS       
        19.5: A 13.7-to-41.5GHz 214.1dBc/Hz FoMT Quad-Core Quad-Mode VCO Using an Oscillation-Mode-Splitting Technique       
Session 20 Overview: Machine Learning Accelerators       
        20.1: NVE: A 3nm 23.2TOPS/W 12b-Digital-CIM-Based Neural Engine for High-Resolution Visual-Quality Enhancement on Smart Devices       
        20.2: A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models       
        20.3: A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications       
        20.4: A 28nm Physics Computing Unit Supporting Emerging Physics-Informed Neural Network and Finite Element Method for Real-Time Scientific Computing on Edge Devices       
        20.5: C-Transformer: A 2.6-18.1μJ/Token Homogeneous DNN-Transformer/Spiking-Transformer Processor withBig-Little Network and Implicit Weight Generation for Large Language Models       
        20.6: LSPU: A Fully Integrated Real-Time LiDAR-SLAM SoC with Point-Neural-Network Segmentation and Multi-Level kNN Acceleration       
        20.7: NeuGPU: A 18.5mJ/Iter Neural-Graphics Processing Unit for Instant-Modeling and Real-Time Rendering with Segmented-Hashing Architecture       
        20.8: Space-Mate: A 303.5mW Real-Time Sparse Mixture-of-Experts-Based NeRF-SLAM Processor for Mobile Spatial Computing       
Session 21 Overview: Audio Amplifiers       
        21.1: A 121.7dB DR and -109.0dB THD+N Filterless Digital-Input Class-D Amplifier with an HV Multibit IDAC Using Tri-level Output and Employing a Transition-Rate-Balanced Bidirectional RTDEM Scheme       
        21.2: A 0.81mA, -105.2dB THD+N Class-D Audio Amplifier with Capacitive Feedforward and PWM-Aliasing Reduction for Wide-Band-Effective Linearity Improvement       
        21.3: A -106.3dB THD+N Feedback-After-LC Class-D Audio Amplifier Employing Current Feedback to Enable 530kHz LC-Filter Cut-Off Frequency       
        21.4: A -108dBc THD+N, 2.3mW Class-H Headphone Amplifier with Power-Aware SIMO Supply Modulator       
Session 22 Overview: High Speed Analog-to-Digital Converters       
        22.1: A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer       
        22.2: A 700MHz-BW –164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving <-85dBFS HD3 using Digital Cancellation of DAC Errors       
        22.3: A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking       
        22.4: A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration       
        22.5: A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC       
Session 23 Overview: Energy-Efficient Connectivity Radios       
        23.1: A 44μW IoT Tag Enabling 1μs Synchronization Accuracy and OFDMA Concurrent Communication with Software-Defined Modulation       
        23.2: A 1mm2 Software-Defined Dual-Mode Bluetooth Transceiver with 10dBm Maximum TX Power and -98.2dBm Sensitivity 2.96mW RX Power at 1Mb/s       
        23.3: A Passive Crystal-Less Wi-Fi-to-BLE Tag Demonstrating Battery-Free FDD Communication with Smartphones       
        23.4: A 167μW 71.7dB-SFDR 2.4GHz BLE Receiver Using a Passive Quadrature-Front-End, a Double-Sided Double-Balanced Cascaded Mixer and a Dual-Transformer-Coupled Class-D VCO       
        23.5: A 7.6mW IR-UWB Receiver Achieving -13dBm Blocker Resilience with a Linear RF Front-End       
Session 24 Overview: D-Band/Sub-THz Transmitters and Sensors       
        24.1: A 90-to-180GHz APD-Integrated Transmitter Achieving 18dBm Psat in 28nm CMOS       
        24.2: A Scalable 134-to-141GHz 16-Element CMOS 2D λ/2-Spaced Phased Array       
        24.3: A 236-to-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS       
        24.4: Sub-THz Ruler: Spectral Bistability in a 235GHz Self-Injection-Locked Oscillator for Agile and Unambiguous Ranging       
Session 25 Overview: Innovations from Outside the (ISSCC) Box       
        25.1: Short-Reach Silicon Photonic Interconnects with Quantum Dot Mode Locked Laser Comb Sources       
        25.2: Extreme Wave-Based Metastructures       
        25.3: Toward Exponential Growth of Therapeutic Neurotechnology       
        25.4: Liquid Metal − Polymer Composites for Stretchable Circuits,Soft Machines, and Thermal Management       
Session 26 Overview: Display and User Interaction Technologies       
        26.1: A 600ch 10b Source-Driver IC with a Charge-Modulation DAC Achieving 1-Horizontal Time of 1.5μs Suitable for 240Hz-Frame-Rate Mobile Displays       
        26.2: A Fully Nonlinear Compact 10b Source Driver with Low-Voltage Gamma Slope DAC and Data/Phase Dependent Current Modulation Achieving 2411μm2/Channel for Mobile OLED Displays       
        26.3: Noise Immunity in Capacitive Sensing: Single-Ended AFE Design with Common-Current Subtraction for Mutual- and Self-Capacitance Sensing in 390pF Load       
        26.4: A 620pF-Compensated Dual-Mode Capacitance Readout IC for Sub-Display TSP with VRR Scan       
        26.5: A 977μW Capacitive Touch Sensor with Noise-Immune Excitation Source and Direct Lock-In ADC Achieving 25.2pJ/step Energy Efficiency       
Session 27 Overview: Wireless Power       
        27.1: A Differential Hybrid Class-ED Power Amplifier with 27W Maximum Power and 82% Peak E2E Efficiency for Wireless Fast Charging To-Go       
        27.2: A 6.78-MHz 79.5%-Peak-Efficiency Wireless Power Transfer System using a Wireless Mode-Recognition Technique and a Fully-On/off Class-D Power Amplifier       
        27.3: A 90.8%-Efficiency SIMO Resonant Regulating Rectifier Generating 3 Outputs in a Half Cycle with Distributed Multi-Phase Control for Wirelessly-Powered Implantable Devices       
        27.4: A 13.56MHz Wireless Power Transfer System with Hybrid Voltage-/Current-Mode Receiver and Global Digital-PWM Regulation Achieving 150% Transfer Range Extension and 72.3% End-to-End Efficiency       
        27.5: A Wireless Power Transfer System with Up-to-27.9% Efficiency Improvement under Coupling Coefficient Ranging from 0.1 to 0.39 Based on Phase-Shift/Time-Constant Detection and Hybrid Transmission Power Control       
Session 28 Overview: High-Density Power Management       
        28.1: A Fully Integrated, Domino-Like-Buffered Analog LDO Achieving –28dB Worst-Case Power-Supply Rejection Across the Frequency Spectrum from 10Hz to 1GHz with 50pF On-Chip Capacitance       
        28.2: A 12V-Input 1V-1.8V-Output 94.7%-Peak-Efficiency 685A/cm3-Current-Density Hybrid DC-DC Converter with a Charge Converging Phase       
        28.3: A 12-28V to 0.6-1.8V Ratio-Regulatable Dickson SC Converter with Dual-Mode Phase Misalignment Operations Achieving 93.1% Efficiency and 6A Output       
        28.4: A Monolithic 12.7W/mm2 Pmax, 92% Peak-Efficiency CSCR-First Switched-Capacitor DC-DC Converter       
        28.5: A 94.1%-Efficiency Parallel-SC Hybrid Buck Converter Designed Using VCR-Aware Topology Optimizer for a 4.2A/mm2 Current-Density FoM       
        28.6: An 87% Efficient 2V-Input, 200A Voltage Regulator Chiplet Enabling Vertical Power Delivery in Multi-kW Systems-on-Package       
Session 29 Overview: ICs for Quantum Technologies       
        29.1: A 22nm FD-SOI <1.2mW/Active-Qubit AWG-Free Cryo-CMOS Controller for Fluxonium Qubits       
        29.2: A Cryo-CMOS Controller with Class-DE Driver and DC Magnetic-Field Tuning for Color-Center-Based Quantum Computers       
        29.3: A Cryo-CMOS Receiver with 15K Noise Temperature Achieving 9.8dB SNR in 10μs Integration Time for Spin Qubit Readout       
        29.4: A Cryo-CMOS Quantum Computing Unit Interface Chipset in 28nm Bulk CMOS with Phase-Detection Based Readout and Phase-Shifter Based Pulse Generation       
        29.5: A Portable 14GHz Dual-Mode Pulse and Continuous-Wave Electron Paramagnetic Resonance Spectrometer Using a Subharmonic Direct Conversion Receiver       
Session 30 Overview: Domain-Specific Computing and Digital Accelerators       
        30.1: A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance       
        30.2: A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing       
        30.3: VIP-Sat: A Boolean Satisfiability Solver Featuring 5×12 Variable In-Memory Processing Elements with 98% Solvability for 50-Variables 218-Clauses 3-SAT Problems       
        30.4: A Fully Integrated Annealing Processor for Large-Scale Autonomous Navigation Optimization       
        30.5: A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing       
        30.6: Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing       
Session 31 Overview: Power Converter Techniques       
        31.1: An 83.4%-Peak-Efficiency Envelope-Tracking Supply Modulator Using a Class-G Linear Amplifier and a Single-Inductor Dual-Input-Dual-Output Converter for 200MHz Bandwidth 5G New Radio RF Applications       
        31.2: A Ripple-Less Buck Converter with Sub -21.94dB EVM for 5G Low Earth Orbit Application       
        31.3: A 950ns 0.5-to-5.5V 5G NR RF PA Supply Modulator with Floating Capacitor Control for Symbol Power Tracking       
        31.4: 98.7% Efficiency 1200V-to-48V LLC Converter with CC/CVMode Charging Compliant with EVSE Level 1       
        31.5: A 750mW, 37% Peak Efficiency Isolated DC-DC Converter with 54/18Mb/s Full-Duplex Communication Using a Single Pair of Transformers       
        31.6: A SIDO/DISO VCF-Step-Reconfigurable Continuously Scalable-Conversion-Ratio SC Converter Achieving 91.4%/92.6% Peak Efficiency and Almost-lossless Channel Switching       
        31.7: A 3.6W 16V-Output 180ns-Response-Time 94%-Efficiency SC Sigma Converter with Output Impedance Compensation and Ripple Mitigation for LiDAR Driver Applications       
        31.8: A 11.7W 9mV/A-Cross-Regulation Single-Inductor Triple-Output Buck Converter Using Unordered Power-Distributive Control for a 2A Load Transient       
        31.9: An 85-264Vac to 3-4.2Vdc 1.05W Capacitive Power Converter with Idle Power Reduction and 4-Phase 1/10X SC Converter Achieving 5.11mW Quiescent Power and 78.2% Peak Efficiency       
        31.10: A Fully integrated 500V, 6.25MHz GaN-IC for Totem-Pole PFC Off-Line Power Conversion       
        31.11: A Capacitor-Based Bias-Flip Rectifier with Electrostatic Charge Boosting for Triboelectric Energy Harvesting Achieving Auto-MPPT at Breakdown Voltage and 14× Power Extraction Improvement       
Session 32 Overview: Power Amplification and Signal Generation       
        32.1: A 47GHz 4-way Doherty PA with 23.7dBm P1dB and 21.7% / 13.1% PAE at 6 / 12dB Back-off Supporting 2000MHz 5G NR 64-QAM OFDM       
        32.2: A 24.25-to-29.5GHz Extremely Compact Doherty Power Amplifier with Differential-Breaking Phase Offset Achieving 23.7% PAEavg for 5G Base-Station Transceivers       
        32.3: A Load-Variation-Tolerant Doherty Power Amplifier with Dual-Adaptive-Bias Scheme for 5G Handsets       
        32.4: A 67.8-to-108.2GHz Power Amplifier with a Three-Coupled-Line-Based Complementary-Gain-Boosting Technique Achieving 442GHz GBW and 23.1% peak PAE       
        32.5: E-band (71-to-86GHz) GaN Power Amplifier with 4.37W Output Power and 18.5% PAE for 5G Backhaul       
        32.6: A 76-to-81GHz Direct-Digital 7b 14GS/s Double-Balanced I/Q Mixing-DAC Radar-Waveform Synthesizer       
        32.7: A 25.2dBm PSAT, 35-to-43GHz VSWR-Resilient Chain-Weaver Eight-Way Balanced PA with an Embedded Impedance/Power Sensor       
        32.8: A 27.8-to-38.7GHz Load-Modulated Balanced Power Amplifier with Scalable 7-to-1 Load-Modulated Power-Combine Network Achieving 27.2dBm Output Power and 28.8%/23.2%/16.3%/11.9% Peak/6/9/12dB Back-Off Efficiency       
        32.9: An Ultra-Compact 28GHz Doherty Power Amplifier with an Asymmetrically-Coupled-Transformer Output Combiner       
        32.10: A Compact Broadband VSWR-Resilient True-Power-and-Gain Sensor with Dynamic-Range Compensation for Phased-Array Applications       
Session 33 Overview: Intelligent Neural Interfaces and Sensing Systems       
        33.1: A High-Accuracy and Energy-Efficient Zero-Shot-Retraining Seizure-Detection Processor with Hybrid-Feature-Driven Adaptive Processing and Learning-Based Adaptive Channel Selection       
        33.2: A Sub-1μJ/class Headset-Integrated Mind Imagery and Control SoC for VR/MR Applications with Teacher-Student CNN and General-Purpose Instruction Set Architecture       
        33.3: MiBMI: A 192/512-Channel 2.46mm2 Miniaturized Brain-Machine Interface Chipset Enabling 31-Class Brain-to-Text Conversion Through Distinctive Neural Codes       
        33.4: A Multi-Loop Neuromodulation Chipset Network with Frequency-Interleaving Front-End and Explainable AI forMemory Studies in Freely Behaving Monkeys       
        33.5: Closed-Loop 100-Channel Highly-Scalable Retinal Implant with 1.02μW Analog ED-Based Adaptive-Threshold Spike Detection and Poisson-Coded Temporally Distributed Optogenetic Stimulation       
        33.6: A Millimetric Batteryless Biosensing and Stimulating Implant with Magnetoelectric Power Transfer and 0.9pJ/b PWM Backscatter       
        33.7: An Adhesive Interposer-Based Reconfigurable Multi-Sensor Patch Interface with On-Chip Application Tunable Time-Domain Feature Extraction       
        33.8: A Two-Electrode Bio-Impedance Readout IC with Complex-Domain Noise-Correlated Baseline Cancellation Supporting Sinusoidal Excitation       
        33.9: A Miniature Neural Interface Implant with a 95% Charging Efficiency Optical Stimulator and an 81.9dB SNDR ΔΣM-Based Recording Frontend       
        33.10: A 2.7ps-ToF-Resolution and 12.5mW Frequency-domain NIRS Readout IC with Dynamic Light Sensing Frontend and Cross-Coupling-Free Inter-Stabilized Data Converter       
        33.11: A Hybrid Recording System with 10kHz-BW 630mVPP 84.6dB-SNDR 173.3dB-FOMSNDR and 5kHz-BW 114dB-DR for Simultaneous ExG and Biocurrent Acquisition       
Session 34 Overview: Compute-In-Memory       
        34.1: A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for High-Accuracy AI Applications       
        34.2: A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices       
        34.3: A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs       
        34.4: A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell       
        34.5: A 818-4094TOPS/W Capacitor-Reconfigured CIM Macro for Unified Acceleration of CNNs and Transformers       
        34.6: A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC       
        34.7: A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing       
        34.8: A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices       
        34.9: A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process


吃个瓜 6.6的稿子遇到什么问题了？

孤岛巨象

有几个Session 文件太大上传失误，以下是整理压缩后的
Session 6  Imagers and Ultrasound
Session 8 Hybrid DC-DC Converters
Session 10  Frequency Synthesis
Session 14 Digital Techniques for System Adaptation, Power Management and Clocking
Session 17 Emerging Sensing and Computing Technologies
Session 20 Machine Learning Accelerators
Session 31 Power Converter Techniques
Session 32 Power Amplification and Signal Generation
Session 33 Intelligent Neural Interfaces and Sensing Systems
Session 34 Compute-In-Memory

smrecnik

thanks

subofu1998

lz没有 session10，麻烦再上传一下呗，谢谢了

houqinghui9

没有8

deepcore

Good job!! Thanks for your general sharing

houqinghui9

有漏部分

自由度

请问有 session8么，非常感谢

raindian

6.6的可能问题在CFP里面有： ISSCC may withdraw any paper that violates the pre-publication guidelines.

raindian

帮楼主补一下漏掉的Session8和10

chuntian101

不全么