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DRC和LVS 的ERC都过了，但是LVS的comparision result 一直有问题
附上LVS report
##################################################
## ##
## C A L I B R E S Y S T E M ##
## ##
## L V S R E P O R T ##
## ##
##################################################
REPORT FILE NAME: LNA_new.lvs.report
LAYOUT NAME: /home/IC/LNA_new.sp ('LNA_new')
SOURCE NAME: /home/IC/LNA.src.net ('LNA')
RULE FILE: /home/IC/_calibre.lvs_
CREATION TIME: Mon Dec 4 09:12:47 2023
CURRENT DIRECTORY: /home/IC
USER NAME: IC
CALIBRE VERSION: v2019.3_15.11 Tue Jul 2 12:24:58 PDT 2019
OVERALL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of nets.
Error: Different numbers of instances.
Error: Connectivity errors.
Error: Property errors.
Warning: Unbalanced smashed mosfets were matched.
**************************************************************************************************************
CELL SUMMARY
**************************************************************************************************************
Result Layout Source
----------- ----------- --------------
INCORRECT LNA_new LNA
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
// LVS COMPONENT TYPE PROPERTY
// LVS COMPONENT SUBTYPE PROPERTY
// LVS PIN NAME PROPERTY
LVS POWER NAME "VDD"
LVS GROUND NAME "VSS"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES ALL
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES YES
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP YES
LVS ALL CAPACITOR PINS SWAPPABLE YES
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC YES
LVS EXPAND UNBALANCED CELLS YES
LVS FLATTEN INSIDE CELL NO
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS YES
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
// LVS SPICE EXCLUDE CELL SOURCE
// LVS SPICE EXCLUDE CELL LAYOUT
LVS SPICE IMPLIED MOS AREA NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES NO
LVS SPICE SCALE X PARAMETERS NO
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES NO
LVS EXACT SUBTYPES NO
LAYOUT CASE NO
SOURCE CASE NO
LVS COMPARE CASE NO
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM 50
LVS PROPERTY RESOLUTION MAXIMUM 32
// LVS SIGNATURE MAXIMUM
// LVS FILTER UNUSED OPTION
// LVS REPORT OPTION
LVS REPORT UNITS YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// LVS IGNORE DEVICE PIN
// LVS PREFER NETS FILTER SOURCE
// LVS PREFER NETS FILTER LAYOUT
LVS PREFER PORT NETS NO
// Reduction
LVS REDUCE SERIES MOS NO
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS NO
LVS REDUCE SPLIT GATES YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS YES
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCE rpodrpo_m PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rpodrpo_m SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rnodrpo_m PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rnodrpo_m SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rpodw_m PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rpodw_m SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rnodw_m PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rnodw_m SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rnwod_m PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rnwod_m SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rpod_m PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rpod_m SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rnod_m PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rnod_m SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rnpo1rpo_dis PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rnpo1rpo_dis SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rppo1rpo_dis PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rppo1rpo_dis SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rnpo1w_dis PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rnpo1w_dis SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rppo1w_dis PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rppo1w_dis SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rppo1_dis PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rppo1_dis SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rnpo1_dis PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rnpo1_dis SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rppolyhri_dis PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rppolyhri_dis SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCTION PRIORITY PARALLEL
LVS SHORT EQUIVALENT NODES NO
// Trace Property
TRACE PROPERTY mn(n2) l l 0
TRACE PROPERTY mn(n2) w w 0
TRACE PROPERTY mn(nb) l l 0
TRACE PROPERTY mn(nb) w w 0
TRACE PROPERTY mn(nd) l l 0
TRACE PROPERTY mn(nd) w w 0
TRACE PROPERTY mn(nl) l l 0
TRACE PROPERTY mn(nl) w w 0
TRACE PROPERTY mn(nn) l l 0
TRACE PROPERTY mn(nn) w w 0
TRACE PROPERTY mn(n) l l 0
TRACE PROPERTY mn(n) w w 0
TRACE PROPERTY mn(n1) l l 0
TRACE PROPERTY mn(n1) w w 0
TRACE PROPERTY mn(na) l l 0
TRACE PROPERTY mn(na) w w 0
TRACE PROPERTY mp(p) l l 0
TRACE PROPERTY mp(p) w w 0
TRACE PROPERTY mp(pa) l l 0
TRACE PROPERTY mp(pa) w w 0
TRACE PROPERTY mp(pd) l l 0
TRACE PROPERTY mp(pd) w w 0
TRACE PROPERTY q(p1) a a 0
TRACE PROPERTY q(pv) a a 0
TRACE PROPERTY q(nv) a a 0
TRACE PROPERTY d(dn) a a 0
TRACE PROPERTY d(dw) a a 0
TRACE PROPERTY d(dp) a a 0
TRACE PROPERTY d(d1) a a 0
TRACE PROPERTY d(d2) a a 0
TRACE PROPERTY d(d3) a a 0
TRACE PROPERTY r(nr) r r 0
TRACE PROPERTY r(m3) r r 0
TRACE PROPERTY r(ns) r r 0
TRACE PROPERTY r(mt) r r 0
TRACE PROPERTY r(m4) r r 0
TRACE PROPERTY r(pr) r r 0
TRACE PROPERTY r(ps) r r 0
TRACE PROPERTY r(wr) r r 0
TRACE PROPERTY r(m1) r r 0
TRACE PROPERTY r(lr) r r 0
TRACE PROPERTY r(m2) r r 0
TRACE PROPERTY c(m3) c c 0
TRACE PROPERTY c(m4) c c 0
TRACE PROPERTY rnpo1rpo_dis w w 0
TRACE PROPERTY rnpo1rpo_dis l l 0
TRACE PROPERTY rppolyhri_rf w w 0
TRACE PROPERTY rppolyhri_rf l l 0
TRACE PROPERTY moscap_rf33 g g 0
TRACE PROPERTY moscap_rf33 b b 0
TRACE PROPERTY pmos_rf33_nw lr lr 0
TRACE PROPERTY pmos_rf33_nw wr wr 0
TRACE PROPERTY pmos_rf33_nw nr nr 0
TRACE PROPERTY rpod_m w w 0
TRACE PROPERTY rpod_m l l 0
TRACE PROPERTY rppo1rpo_dis w w 0
TRACE PROPERTY rppo1rpo_dis l l 0
TRACE PROPERTY rppolyhri_dis w w 0
TRACE PROPERTY rppolyhri_dis l l 0
TRACE PROPERTY rppoly_rf w w 0
TRACE PROPERTY rppoly_rf l l 0
TRACE PROPERTY rppolywo_rf w w 0
TRACE PROPERTY rppolywo_rf l l 0
TRACE PROPERTY mimcap_shield lt lt 0
TRACE PROPERTY mimcap_shield wt wt 0
TRACE PROPERTY mimcap_wos lt lt 0
TRACE PROPERTY mimcap_wos wt wt 0
TRACE PROPERTY nmoscap lr lr 0
TRACE PROPERTY nmoscap wr wr 0
TRACE PROPERTY nmoscap mr mr 0
TRACE PROPERTY rnodw_m w w 0
TRACE PROPERTY rnodw_m l l 0
TRACE PROPERTY nmoscap_33 lr lr 0
TRACE PROPERTY nmoscap_33 wr wr 0
TRACE PROPERTY nmoscap_33 mr mr 0
TRACE PROPERTY lincap lr lr 0
TRACE PROPERTY lincap wr wr 0
TRACE PROPERTY lincap mr mr 0
TRACE PROPERTY rpodw_m w w 0
TRACE PROPERTY rpodw_m l l 0
TRACE PROPERTY spiral_s2_sym_ct lay lay 0
TRACE PROPERTY spiral_s2_sym_ct w w 0
TRACE PROPERTY spiral_s2_sym_ct s s 0
TRACE PROPERTY spiral_s2_sym_ct nr nr 0
TRACE PROPERTY spiral_s2_sym_ct rad rad 0
TRACE PROPERTY spiral_s3_sym_ct lay lay 0
TRACE PROPERTY spiral_s3_sym_ct w w 0
TRACE PROPERTY spiral_s3_sym_ct s s 0
TRACE PROPERTY spiral_s3_sym_ct nr nr 0
TRACE PROPERTY spiral_s3_sym_ct rad rad 0
TRACE PROPERTY spiral_s2_sym lay lay 0
TRACE PROPERTY spiral_s2_sym w w 0
TRACE PROPERTY spiral_s2_sym s s 0
TRACE PROPERTY spiral_s2_sym nr nr 0
TRACE PROPERTY spiral_s2_sym rad rad 0
TRACE PROPERTY spiral_s3_sym lay lay 0
TRACE PROPERTY spiral_s3_sym w w 0
TRACE PROPERTY spiral_s3_sym s s 0
TRACE PROPERTY spiral_s3_sym nr nr 0
TRACE PROPERTY spiral_s3_sym rad rad 0
TRACE PROPERTY xjvar_w40 nr nr 0
TRACE PROPERTY xjvar_w40 w w 0
TRACE PROPERTY rnpo1w_dis w w 0
TRACE PROPERTY rnpo1w_dis l l 0
TRACE PROPERTY rppo1w_dis w w 0
TRACE PROPERTY rppo1w_dis l l 0
TRACE PROPERTY rnpo1_dis w w 0
TRACE PROPERTY rnpo1_dis l l 0
TRACE PROPERTY rnodrpo_m w w 0
TRACE PROPERTY rnodrpo_m l l 0
TRACE PROPERTY rppo1_dis w w 0
TRACE PROPERTY rppo1_dis l l 0
TRACE PROPERTY rpodrpo_m w w 0
TRACE PROPERTY rpodrpo_m l l 0
TRACE PROPERTY xjvar_nr36 nr nr 0
TRACE PROPERTY xjvar_nr36 w w 0
TRACE PROPERTY nmos_rf lr lr 0
TRACE PROPERTY nmos_rf wr wr 0
TRACE PROPERTY nmos_rf nr nr 0
TRACE PROPERTY spiral_s2_std lay lay 0
TRACE PROPERTY spiral_s2_std w w 0
TRACE PROPERTY spiral_s2_std s s 0
TRACE PROPERTY spiral_s2_std nr nr 0
TRACE PROPERTY spiral_s2_std rad rad 0
TRACE PROPERTY spiral_s3_std lay lay 0
TRACE PROPERTY spiral_s3_std w w 0
TRACE PROPERTY spiral_s3_std s s 0
TRACE PROPERTY spiral_s3_std nr nr 0
TRACE PROPERTY spiral_s3_std rad rad 0
TRACE PROPERTY pmos_rf lr lr 0
TRACE PROPERTY pmos_rf wr wr 0
TRACE PROPERTY pmos_rf nr nr 0
TRACE PROPERTY rnwod_m w w 0
TRACE PROPERTY rnwod_m l l 0
TRACE PROPERTY pmos_rf_nw lr lr 0
TRACE PROPERTY pmos_rf_nw wr wr 0
TRACE PROPERTY pmos_rf_nw nr nr 0
TRACE PROPERTY nmos_rf33 lr lr 0
TRACE PROPERTY nmos_rf33 wr wr 0
TRACE PROPERTY nmos_rf33 nr nr 0
TRACE PROPERTY moscap_rf g g 0
TRACE PROPERTY moscap_rf b b 0
TRACE PROPERTY pmos_rf33 lr lr 0
TRACE PROPERTY pmos_rf33 wr wr 0
TRACE PROPERTY pmos_rf33 nr nr 0
TRACE PROPERTY rnod_m w w 0
TRACE PROPERTY rnod_m l l 0
CELL COMPARISON RESULTS ( TOP LEVEL )
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of nets (see below).
Error: Different numbers of instances (see below).
Error: Connectivity errors.
Error: Property errors.
Warning: Unbalanced smashed mosfets were matched.
LAYOUT CELL NAME: LNA_new
SOURCE CELL NAME: LNA
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 8 8
Nets: 28 26 *
Instances: 110 14 * MN (4 pins)
223 20 * MP (4 pins)
36 2 * C (2 pins)
8 8 R (2 pins)
------ ------
Total Inst: 377 44
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 8 8
Nets: 24 21 *
Instances: 11 11 MN (4 pins)
15 11 * MP (4 pins)
2 2 C (2 pins)
3 3 R (2 pins)
1 2 * SMP2 (4 pins)
1 1 _smn2v (4 pins)
------ ------
Total Inst: 33 30
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT NETS
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 Net VDD VDD
--- 26 Connections On This Net --- --- 22 Connections On This Net ---
-------------------------- --------------------------
X196/X0/M0(-351.945,-117.130):b ** missing connection **
X93/M0(-245.860,-316.695):b ** missing connection **
X92/M0(-279.615,-316.670):b ** missing connection **
X87/X0/X0/M0(-206.010,-128.470):b ** missing connection **
X87/X0/X0/M0(-206.010,-128.470):s ** missing connection **
** missing connection ** MM15:s
--------------------------------------------------------------------------------------------------------------
2 Net IREF IREF
--- 9 Connections On This Net --- --- 9 Connections On This Net ---
-------------------------- --------------------------
X87/X0/X0/M0(-206.010,-128.470):g ** missing connection **
** missing connection ** MM15:g
--------------------------------------------------------------------------------------------------------------
3 Net 4 VO1
--- 3 Connections On This Net --- --- 3 Connections On This Net ---
-------------------------- --------------------------
X140/X0/M0(-300.950,-316.695):d ** missing connection **
** missing connection ** (SMP2) utput
MM4:d
--------------------------------------------------------------------------------------------------------------
4 Net 12 net03
--- 3 Connections On This Net --- --- 3 Connections On This Net ---
-------------------------- --------------------------
X93/M0(-245.860,-316.695):d ** missing connection **
X92/M0(-279.615,-316.670):d ** missing connection **
** missing connection ** MM16:s
** missing connection ** MM17:s
--------------------------------------------------------------------------------------------------------------
5 Net 15 net6
--- 5 Connections On This Net --- --- 5 Connections On This Net ---
-------------------------- --------------------------
X140/X0/M0(-300.950,-316.695):g ** missing connection **
** missing connection ** (SMP2):input
MM4:g
--------------------------------------------------------------------------------------------------------------
6 Net 10 ** missing net **
--------------------------------------------------------------------------------------------------------------
7 Net 11 ** missing net **
--------------------------------------------------------------------------------------------------------------
8 Net 22 ** missing net **
**************************************************************************************************************
INCORRECT INSTANCES
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
9 X87/X0/X0/M0(-206.010,-128.470) MP(P) ** missing instance **
--------------------------------------------------------------------------------------------------------------
10 X92/M0(-279.615,-316.670) MP(P) ** missing instance **
--------------------------------------------------------------------------------------------------------------
11 X93/M0(-245.860,-316.695) MP(P) ** missing instance **
--------------------------------------------------------------------------------------------------------------
12 X196/X0/M0(-351.945,-117.130) MP(P) ** missing instance **
--------------------------------------------------------------------------------------------------------------
13 ** missing gate ** (SMP2)
Transistors:
MM2 MP(P)
MM4 MP(P)
**************************************************************************************************************
PROPERTY ERRORS
DISC# LAYOUT SOURCE ERROR
**************************************************************************************************************
14 X140/X0/M0(-300.950,-316.695) MP(P) MM15 MP(P)
w: 645 u w: 800 u 19.4%
15 X167/M0(-401.605,-117.130) MP(P) MM16 MP(P)
w: 600 u w: 640 u 6.25%
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 8 8 0 0
Nets: 21 21 3 0
Instances: 11 11 0 0 MN(N)
11 11 4 0 MP(P)
2 2 0 0 C(M4)
1 1 0 0 R(NR)
2 2 0 0 R(WR)
1 1 0 1 SMP2
1 1 0 0 _smn2v
------- ------- --------- ---------
Total Inst: 29 29 4 1
o Statistics:
331 layout mos transistors were reduced to 28.
303 mos transistors were deleted by parallel reduction.
8 source mos transistors were reduced to 2.
6 mos transistors were deleted by parallel reduction.
36 parallel layout capacitors were reduced to 2.
8 series/parallel layout resistors were reduced to 3. 2 connecting nets were deleted.
8 series/parallel source resistors were reduced to 3. 2 connecting nets were deleted.
o Initial Correspondence Points:
Ports: VDD VSS VOUT1 VOUT2 IREF VOUTCM VIN- VIN+
o Matched Mosfets Which Have Been Unequally Reduced:
X66/X0/M0(-137.725,-132.920) MM35
X186/X0/M0(-409.245,-75.250) MM27
X185/X0/M0(-409.245,-117.130) MM28
X173/M0(-344.305,-75.250) MM29
X172/M0(-344.305,-117.130) MM31
X124/X1/M0(-283.380,-86.470) MM34
X120/X0/M0(-317.760,-86.470) ** missing smashed mosfet **
X111/X1/M0(-202.480,-233.835) ** missing smashed mosfet **
X110/X1/M0(-202.480,-316.695) ** missing smashed mosfet **
X97/X0/M0(-284.420,-233.835) ** missing smashed mosfet **
X91/M0(-284.420,-316.695) ** missing smashed mosfet **
X76/X1/X1/X1/M0(-333.725,-17.790) ** missing smashed mosfet **
X75/M0(-144.890,-128.470) ** missing smashed mosfet **
X74/M0(-270.825,-128.470) ** missing smashed mosfet **
X72/X0/M0(-100.705,-17.790) ** missing smashed mosfet **
X71/X1/M0(-101.205,-132.920) ** missing smashed mosfet **
X4/M0(-19.285,-127.015) MM33
X129/X1/M0(-285.020,-113.355) MM32
X125/X0/M0(-314.900,-113.355) ** missing smashed mosfet **
X24/X0/M0(-92.725,-72.315) ** missing smashed mosfet **
X23/X0/M0(-92.725,-127.015) ** missing smashed mosfet **
X5/M0(-19.285,-72.315) ** missing smashed mosfet **
**************************************************************************************************************
DETAILED INSTANCE CONNECTIONS
LAYOUT NAME SOURCE NAME
**************************************************************************************************************
(This section contains detailed information about connections of
matched instances that are involved in net discrepancies).
--------------------------------------------------------------------------------------------------------------
X140/X0/M0(-300.950,-316.695) MP(P) MM15 MP(P)
s: 12 d: net03
b: VDD b: VDD
g: 15 ** net6 **
d: 4 ** VO1 **
** IREF ** g: IREF
** VDD ** s: VDD
--------------------------------------------------------------------------------------------------------------
X167/M0(-401.605,-117.130) MP(P) MM16 MP(P)
g: 26 g: vcm
d: 20 d: Vn2
b: VDD b: VDD
s: 10 ** missing net **
** 12 ** s: net03
--------------------------------------------------------------------------------------------------------------
X168/M0(-401.605,-75.250) MP(P) MM17 MP(P)
g: VOUTCM g: VOUTCM
d: 21 d: net033
b: VDD b: VDD
s: 10 ** missing net **
** 12 ** s: net03
**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total CPU Time: 0 sec
Total Elapsed Time: 0 sec
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发表于 2023-12-4 10:15:13
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