#IFDEF HIGH_VLOTAGE_DS_CHECK
pmosvdd33 { @ pmos_sd connected to 3.3vpower is not allow but the voltage potentail difference of Vds Vgs Vgd <=1.8v can waive //@说明句式,表示如果Vds Vgs Vgd的压差小于1.8v可以忽略
pthin_18 = nxwell AND ((( mdiff AND PP ) AND OD18 ) NOT RH_OD ) //定义pmos的有源区
NET pthin_18 HVPOWER_NAME //采用NET表示pthin_18上如果接入了标记有“VDDPST33" 的金属走线,那么结果会报错。
}
#ENDIF
在这里还有个疑问,想请教各位:规则写入pthin_18 = nxwell AND ((( mdiff AND PP ) AND OD18 ) NOT RH_OD )有输出结果,但是layer换个顺序比如:pthin_18 = RH_OD AND ((( mdiff AND PP ) AND OD18 ) NOT nxwell )就会报错“cannot establish connectivity of this layer in the MASK connectivity set pthin_18”,这个逻辑是什么为什么会这样我还没搞明白。