Low-Noise Amplifier with ESD Protection

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New Matching Methodology of Low-Noise Amplifier with ESD Protection

Bo-Shih Huang
ESD and Product Engineering Department
SoC Center, ITRI
Hsinchu, Taiwan, R.O.C.
huangboshi@itri.org.tw
Ming-Dou Ker
Nanoelectronics and Gigascale Systems Laboratory
National Chiao-Tung University
Hsinchu, Taiwan, R.O.C.
mdker@ieee.org


Abstract

A new matching design of Low-Noise Amplifier (LNA) with ESD protection is proposed and implemented in an ESD-protected LNA, which manipulates the parasitic capacitance of ESD protection device as a core part of LNA matching network. Without significant degradation on RF performance, 4.5-kV Human-Body-Model (HBM) and 250-V Machine-Model (MM) ESD levels can be achieved. The low RF-performance degradation and high ESD immunity can be simultaneously realized in a simple matching structure without extra circuit components dealing with ESD parasitics in a multi-GHz LNA.

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INTRODUCTION
RF IC rapidly evolves in wireless communication during recent years. Every IC product has to include ESD protection for good production yield and reliability, so does RF IC. LNA is located on the front stage of RF receiver and usually equipped with on-chip ESD protection circuit. Inducing parasitics such as dominant parasitic capacitance, ESD protection device may severely degrade the RF performance. To alleviate such influence, co-design strategies of LNA with ESD protection have been developed. Low-capacitance ESD devices with power-rail ESD clamp circuit has been proved as an effective solution [1]. As LNA operates at higher frequencies, another bottleneck emerges. Parasitic capacitance of proper-sized ESD protection devices cannot be reduced unlimitedly. The limitation causes difficult trade-off between RF performance and ESD immunity. Since ESD device is attached to the input-signal path of LNA, input matching becomes a challenge in LNA that operates at frequency of multi-GHz

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CONCLUSIONS
A new matching methodology of LNA with ESD protection was implemented and verified in a 2.4-GHz LNA. The matching methodology conceptually combines the parasitic capacitance into the input matching network of core LNA circuit without complicating the matching structure. The main advantages are avoiding significant RF-performance degradation, omitting extra circuit components, and saving chip area. The experimental results unveil an achievement that a multi-GHz LNA can perform high ESD immunity of 4.5-kV HBM and 250-V MM levels without significant RF degradation due to ESD protection devices. This new matching design leads to a simple and effective solution of LNA with ESD protection.

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REFERENCES [1] M.-D. Ker, W.-Y. Lo, C.-M. Lee, C.-P. Chen, and H.-S. Kao, “ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness,” Proc. of IEEE RFIC Symposium, 2002, pp. 427-430. [2] D. K. Shaeffer and T. H. Lee, The design and implementation of low-power CMOS radio receivers, Boston, Kluwer, 1999. [3] V. Chandrasekhar, C. M. Hung, Y. C. Ho, and K. Mayaram, “A packaged 2.4-GHz LNA in 0.15μm CMOS process with 2kV HBM ESD protection,” Proc. of ESSCIRC, 2002, pp. 347-350. [4] P. Leroux and M. Steyaert, “A 5 GHz CMOS low-noise amplifier with inductive ESD protection exceeding 3 kV HBM,” Proc. of ESSCIRC, 2004, pp. 295-298. [5] M.-D. Ker, “Area-efficient VDD-to-VSS ESD clamp circuit by using substrate-triggering field-oxide device (STFOD) for whole-chip ESD protection,” Proc. of International Symposium on VLSI Technology, Systems, and Applications, 1997, pp. 69-73. [6] Electrostatic discharge (ESD) sensitivity testing — human body model (HBM), International Standard, JEDEC EIA/JESD22-A114-B, 2000. [7] Electrostatic discharge (ESD) sensitivity testing — machine model (MM), International Standard, JEDEC EIA/JESD22-A115-A, 1997.

flyfeng

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hanyang

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cloudgood123

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copylife

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iyahsue

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巫山傍水

回复 4# semico_ljj


thank u very much.fine .