Startpoint: seed[13] (input port clocked by clk2)
Endpoint: RAND_CORE_U16_RAND_CODE_REG_13_
(rising edge-triggered data to data check clocked by clk2)
Path Group: clk2
Path Type: max
Max Data Paths Derating Factor : 1.00
Min Clock Paths Derating Factor : 0.90
Max Clock Paths Derating Factor : 1.00
Point Incr Path
------------------------------------------------------------------------------
clock clk2 (rise edge) 0.00 0.00
clock network delay (propagated) 0.84 0.84
input external delay 0.80 1.64 f
seed[13] (in) 0.05 & 1.69 f
U1676/Z (NID1) 0.19 & 1.87 f
U1699/Z (DL200) 1.76 & 3.63 f
U772/Z (ND2D0) 0.18 & 3.81 r
RAND_CORE_U16_RAND_CODE_REG_13_/SN (FD4D1) 0.00 & 3.81 r
data arrival time 3.81
clock clk2 (rise edge) 0.00 0.00
clock network delay (propagated) 0.75 0.75
clock reconvergence pessimism 0.00 0.75
input external delay 0.20 0.95 r
seed[13] (in) 0.04 & 0.99 r
U1676/Z (NID1) 0.16 & 1.15 r
U1699/Z (DL200) 1.38 & 2.54 r
U773/Z (OR2D0) 0.19 & 2.73 r
RAND_CORE_U16_RAND_CODE_REG_13_/RN (FD4D1) 0.00 & 2.73 r
data check setup time -0.11 2.62
data required time 2.62
------------------------------------------------------------------------------
data required time 2.62
data arrival time -3.81
------------------------------------------------------------------------------
slack (VIOLATED) -1.19