VCS仿真XILINX的HBM IP：Error-[URMI] Unresolved modules

efons

各位大佬好！

求助一下关于使用VCS仿真Xilinx的HBM IP时遇到的ERROR，

用Vivado Export Simulation后执行.sh文件在elaborate步骤出现了以下错误：

Error-[URMI] Unresolved modules
./../111/111.srcs/sources_1/ip/hbm_0/hdl/rtl/hbm_v1_0_7.sv, 2280
" IBUF ONE_STACK.u_HBM_REF_CLK_IBUF_0( .I (HBM_REF_CLK_0),  .O (HBM_REF_CLK_0_ibuf));"
  Module definition of above instance is not found in the design.


Error-[URMI] Unresolved modules
./../111/111.srcs/sources_1/ip/hbm_0/hdl/rtl/hbm_v1_0_7.sv, 2288
" BUFG ONE_STACK.u_HBM_REF_CLK_BUFG_0( .I (HBM_REF_CLK_0_ibuf),  .O (HBM_REF_CLK_0_bufg));"
  Module definition of above instance is not found in the design.


Error-[URMI] Unresolved modules
./../111/111.srcs/sources_1/ip/hbm_0/hdl/rtl/hbm_v1_0_7.sv, 2477
" hbm_top #(.HBM_STACK(HBM_STACK), .SWITCH_ENABLE_00(SWITCH_ENABLE_00), .SWITCH_ENABLE_01(SWITCH_ENABLE_01), .INIT_BYPASS(INIT_BYPASS), .INIT_SEQ_TIMEOUT(INIT_SEQ_TIMEOUT), .AXI_RST_ASSERT_WIDTH(AXI_RST_ASSERT_WIDTH), .AXI_RST_DEASSERT_WIDTH(AXI_RST_DEASSERT_WIDTH), .TEMP_WAIT_PERIOD_0(TEMP_WAIT_PERIOD_0), .TEMP_WAIT_PERIOD_1(TEMP_WAIT_PERIOD_1), .SWITCH_EN_0(SWITCH_EN_0), .SWITCH_EN_1(SWITCH_EN_1), .AXI_CLK_FREQ(AXI_CLK_FREQ), .AXI_CLK1_FREQ(AXI_CLK1_FREQ), .HBM_REF_CLK_FREQ_0(HBM_REF_CLK_FREQ_0), .HBM_REF_CLK_FREQ_1(HBM_REF_CLK_FREQ_1), .HBM_CLK_FREQ_0(HBM_CLK_FREQ_0), .HBM_CLK_FREQ_1(HBM_CLK_FREQ_1), .HBM_STACK_NUM(HBM_STACK_NUM), .CLK_SEL_00(CLK_SEL_00), .CLK_SEL_01(CLK_SEL_01), .CLK_SEL_02(CLK_SEL_02), .CLK_SEL_03(CLK_SEL_03), .CLK_SEL_04(CLK_SEL_04 ... "
  Module definition of above instance is not found in the design.
3 errors
CPU time: .311 seconds to compile

common elaboration failed
./tb_test.sh: line 103: ./tb_test_simv: No such file or directory


拜托各位了！

foy

编译的文件列表看下，没编译这些lib和ip的仿真文件啊

efons

foy 发表于 2023-4-11 09:32
编译的文件列表看下，没编译这些lib和ip的仿真文件啊

换了个盘跑就解决了。。。