|
马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
In this course, you
● Identify and apply timing arc information from a library, such as uniqueness, delays, and slew
● Identify cell delays from a library and calculate output slew degradation
● Use wire-load information to calculate net delays
● Identify the properties of a clock, including period, edges, and slew, and calculate the duty cycle
● Apply setup and hold checks to diagnose design violations
● Identify timing path types to calculate slack values
● Set environmental constraints, clocks constraints, and path exceptions
● Constrain a design using SDC
● Analyze reports to identify timing problems
|
-
net
-
-
STA.pdf
3.07 MB, 下载次数: 190
, 下载积分:
资产 -2 信元, 下载支出 2 信元
STA
|