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发表于 2009-5-24 08:31:11
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This paper presents a survey of the principal architectures and
blocks building up a Flash memory, describing how these blocks
are designed and how their design has changed over the years to
satisfy the new specification requests. For example, the continuous
supply voltage reduction aimed at portable electronic solutions has
forced designers to find innovative design solutions. An overview
of the test modes developed for the Flash device not only to debug
the chip but also to try to improve reliability is given. Ad hoc test
modes are useful to deeply increase the analysis capability. Finally,
the test methodology for Flash memories, a challenge between the
test time reduction and better test coverage, is presented.
Keywords—Access time, automatic test equipment (ATE), boost,
charge pump, chip-scaled package (CSP), decoders, dual in-line
(DIL), direct memory access (DMA), drain stress, electrical stress,
erasable programmable ROM (EPROM), electrical wafer sort
(EWS), finite-state machine (FSM), Flash memory, Fourier transform,
gate stress, matrix organization, one-time programmable
(OTP), reference, sector, test modes, triple well, unerasable
programmable ROM (UPROM), voltage regulator. |
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发表于 2008-11-3 09:37:58
