PowerPlanning in ASIC

smc1017

Could you give me some advice for PowerPlanning Part (Such as how to choose the Power Ring Width, how many sets of them, and the stripe width/spacing ...)

smc1017

I have found this

smc1017

Thanks for your kind words and your very good question.
Unfortunately, my answer is more towards the "black magic" one...
So there are rings for VDD/GND inside the pads and essentially, you "don't need" the core rings for power distribution. Of course, they help, but I believe that their main purpose/use is to ease the connections to the follow pins and power stripes, because the rings inside the pads are inaccessible. That being said, I've seen a floorplan without core rings at all, but this makes connecting really hard.

For the spacing - you actually want VDD/GND to be close to each other for decap. So your only constraints are the spacing of the vias for connection to the pad pins on one side and the follow pins/stripes on the other side. These can be tricky, because of harder and harder design rules at scaled technologies, but you'll see them quickly during floorplanning DRC run. As for width - yes, the only real way to do this is run Voltus (or other tool) early rail analysis (I don't discuss this in the course and I am far from an expert - it didn't exist when I was in industry). These tools tell you if you have a robust power grid or you have "hot spots" that you need to address. But, as I mentioned, there is a lot of black magic involved. In our lab, we got some guidance from Cadence and kind of blindly follow it (though we're not making products, so we don't care too much...) and so I recently asked a friend in Industry who has worked at both big big (BIG) companies and is currently at a start up and his answer was no better. At the big company, there was a design technologies team that told the backend teams what to do in terms of power grid and then run Voltus to see that it was okay. In the start up, they kind of guess. So there is no good answer that I know of, but at least nowadays, the tools help you identify problems. When I worked at Marvell, this wasn't the case and there were a few huge "disasters" due to IR Drop. Consequently, we had power grids that were so thick, you could barely route your design, resulting in low utilization and extreme routing run times (and gray hair...). We literally needed permission from the head of the design technology team to cut a power rail to enable routing, because they were so scared of an IR failure. They had internal scripts that ran rail analysis, but they took days to run and the commercial tools didn't provide this. The situation today is much better.

cabal2012

Thanks

bushi志强

Thanks

sdcxx

thank

赢闪闪

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