使用vcs仿真UPF时遇到问题

luzi

我使用dc对verilog.v和upf_verilog.upf进行综合生成了netlist_dc.v和upf_dc.upf。在使用vcs对netlist_dc.v和upf_dc.upf进行仿真时出现错误。这是vcs脚本
run:
    vcs -full64 -sverilog \
    -l run.log -f run.f -upf ../../syn_verilog/report/top_gates.upf \
    -P $(VERDI_FSDB)/novas.tab \
    $(VERDI_FSDB)/pli.a -R -debug_all -lca -power_top TOP
这是vcs的错误信息
[0 ps] [INFO] [LP_PPN_STATE_CHANGE] State of the primary power net 'VDD_SW' of power domain 'testbench/u_top/TOP_A4' changed from OFF to UNDETERMINED.
[0 ps] [WARNING] [LP_PST_INIT_ILLEGAL] Design started with 'ILLEGAL' state (illegal) in pst 'testbench/u_top/power_state'.
[0 ps] [ERROR] [LP_PSW_CTRL_INIT_INVALID] Signal 'testbench/u_top/A5/B_SW' connected to control port 'E' of power switch 'testbench/u_top/A4_SW' started with an invalid value 'StX'.
[0 ps] [INFO] [LP_PSW_ISP_INIT_STATE] Supply net 'testbench/u_top/VDD' tied to input supply port 'PGVDD' of power switch 'testbench/u_top/A4_SW' started with state FULL_ON.
[0 ps] [INFO] [LP_PSW_ISP_INIT_VALUE] Supply net 'testbench/u_top/VDD' tied to input supply port 'PGVDD' of power switch 'testbench/u_top/A4_SW' started with voltage 1.2 V.
[0 ps] [INFO] [LP_PSW_OSP_INIT_STATE] Supply net 'testbench/u_top/VDD_SW' tied to output supply port 'VDD' of power switch 'testbench/u_top/A4_SW' started with state UNDETERMINED.
[0 ps] [INFO] [LP_PSW_OSP_INIT_VALUE] Supply net 'testbench/u_top/VDD_SW' tied to output supply port 'VDD' of power switch 'testbench/u_top/A4_SW' started with voltage 0 V.
[0 ps] [INFO] [LP_PSW_INIT_STATE] Power switch 'testbench/u_top/A4_SW' started in INVALID (ERROR) state.
错误信息好像是power_switch_cell的电压进入了不确定态。
其中TOP的电压加上了，这是vcs的信息[0 ps] [INFO] [LP_PD_INIT_STATE] Power domain 'testbench/u_top/TOP_1' started in 'NORMAL' state.
[0 ps] [INFO] [LP_PPN_INIT_STATE] Primary power net 'VDD' of power domain 'testbench/u_top/TOP_1' started in FULL_ON state.
[0 ps] [INFO] [LP_PGN_INIT_STATE] Primary ground net 'VSS' of power domain 'testbench/u_top/TOP_1' started in FULL_ON state.
[0 ps] [INFO] [LP_PPN_INIT_VALUE] Primary power net 'VDD' of power domain 'testbench/u_top/TOP_1' started with voltage 1.2 V.
[0 ps] [INFO] [LP_PGN_INIT_VALUE] Primary ground net 'VSS' of power domain 'testbench/u_top/TOP_1' started with voltage 0 V.
但是vcs还输出了其他信息说VDD、VSS没有连接：
Lint-[TFIPC-L] Too few instance port connections
../../syn_verilog/report/netlist_dc.v, 13
"AN2M1LM U1( .A (B),  .B (A),  .Z (O));"
  The above instance has fewer port connections than the module definition,
  inout port 'VDD' is not connected,
  inout port 'VSS' is not connected.

感觉好像是domain供上电了，但是里面的cell没有供电。

这是upf_dc.upf中的create_power_switch
create_power_switch A4_SW -domain TOP_A4 \
-output_supply_port {VDD VDD_SW} -input_supply_port {PGVDD VDD} -control_port {E A5/B_SW} \
-on_state {ON PGVDD {E}} -off_state {OFF {!E}}
map_power_switch A4_SW -domain TOP_A4 -lib_cells {PGH2LM}

而且在netlist_dc.v中并没有找到power_switch_cell.只找到了iso_cell。
module TOP ( O1, O2, A, B, C, D, E, IA, clk );
  input A, B, C, D, E, IA, clk;
  output O1, O2;
  wire   O_A1, O_A3, O_A4, B_SW, B_ISO, net4, n1;

  and2_3 A1 ( .O(O_A1), .A(A), .B(B) );
  and2_2 A2 ( .O(O1), .A(C), .B(O_A1) );
  and2_1 A3 ( .O(O_A3), .A(D), .B(E) );
  and2_0 A4 ( .O(net4), .A(O_A3), .B(O_A1) );
  inv2 A6 ( .A(O_A4), .O(O2) );
  pmc A5 ( .A(IA), .clk(clk), .B_SW(B_SW), .B_ISO(B_ISO) );
  ISBM2LM snps_TOP_A4__A4_ISO_snps_O_UPF_ISO ( .A(net4), .EB(n1), .Z(O_A4) ); //synopsys isolation_upf A4_ISO+TOP_A4
  CKINVM1LM U1 ( .A(B_ISO), .Z(n1) );
endmodule

我使用vcs对verilog.v和upf_verilog.upf。并没有出错。
这是vcs脚本
run_v:
    vcs -full64 -sverilog \
    -l run.log -f run_verilog.f -upf verilog.upf \
    -power_top TOP \
    -P $(VERDI_FSDB)/novas.tab \
    $(VERDI_FSDB)/pli.a -R -debug_all -lca

想要询问vcs仿真netlist_dc.v和upf_dc.upf为什么出错，以及怎么修改。

三岁就十分拽

需要调库的 就是撰写low power config文件 详见附件

luzi

三岁就十分拽 发表于 2022-11-19 11:39
需要调库的 就是撰写low power config文件 详见附件

非常感谢，卡了我快一个月了，一直以为是UPF或者dc的脚本写错了。没想到是vcs的问题。

luzi

三岁就十分拽 发表于 2022-11-19 10:44
需要调库的 就是撰写low power config文件 详见附件

我发现vcs可以运行网表文件了，但是还是会报错，虽然这个报错并不影响结果。
报的错误还是说进入Stx态：
[0 ps] [INFO] [LP_PPN_STATE_CHANGE] State of the primary power net 'VDD_SW' of power domain 'testbench/u_top/TOP_A4' changed from OFF to UNDETERMINED.
[0 ps] [WARNING] [LP_PST_INIT_ILLEGAL] Design started with 'ILLEGAL' state (illegal) in pst 'testbench/u_top/power_state'.
[0 ps] [ERROR] [LP_PSW_CTRL_INIT_INVALID] Signal 'testbench/u_top/A5/B_SW' connected to control port 'E' of power switch 'testbench/u_top/A4_SW' started with an invalid value 'StX'.
[0 ps] [INFO] [LP_PSW_ISP_INIT_STATE] Supply net 'testbench/u_top/VDD' tied to input supply port 'PGVDD' of power switch 'testbench/u_top/A4_SW' started with state FULL_ON.
我看了下波形，好像是因为cell的延时问题，但是我的tb文件没有加sdf文件，这是pmc的vcs的波形：

这是pmc综合前的内容：
module pmc (input A,output B_SW,B_ISO);
//可以考虑通过记录clk的周期数来更改输出。
wire A;
reg B_SW,B_ISO;
always@(A)
begin
if(!A)
begin
B_SW<=1'b0;
B_ISO<=1'b0;
end
else
begin
B_SW<=1'b1;
B_ISO<=1'b1;
end
end


虽然这个error并没有影响后续的vcs波形，但是这个提示的error是怎么回事，以及怎么修正掉？