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本帖最后由 2046 于 2022-11-8 17:35 编辑
In this work, we focus on the ECC systems, due to the similar security level promised with significantly smaller key lengths compared with RSA. However, software implementations of ECC algorithms on flash memory controllers may result in unacceptable computational latency. To reduce the computational latency to an acceptable range of a few milliseconds, we present hardware architectures optimized for the ECC operations targeting a low area. We propose an ECC processor design for Gaussian integers that is a competitive solution for applications in resource-constrained embedded systems such as flash memory controllers.
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