Digital System Design using FSMs @2021

2046 · 发表于 2022-10-26 23:18:47

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本帖最后由 2046 于 2022-11-8 13:29 编辑

This book is, in large part, a development of FSM‐Based Digital Design using verilog hdl (Minns and EllIOTt 2008), a book I wrote with Ian Elliott. It is rather unusual in that it forms a linear programmed learning text in all chapters to help readers learn on their own.

The intention in this current version is to make use of programmed learning methods in which the chapters are made up of frames that must be read in a sequen- tial manner. It is hoped that the book will help readers in their study of the material. There is also new content in Chapter 6, Appendix A5, and Appendix A6, as well as consideration of unused states in finite state machines (FSMs).

It is assumed that the reader has a good understanding of Verilog HDL; however, the interested reader will find that Chapters 6, 7, and 8 of Minns and Elliott (2008) provide a very good account of Verilog HDL.