USB3.1SSP+/DP Alt PHY 特点和描述

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Type-C - USB3.1SSP+/DPAlt PHY provides fullduplex transceiver pair for USB and a maximum 4 Transmit lanes for DP or HDMI operation and consists of the following:
■ A hard macro (physical medium attachment (PMA)/SerDes)
■ A soft RTL module (raw physical coding sublayer (PCS):
The PHY provides the following features:
■ Highly customizable physical medium attachment (PMA) configuration (controlled by PCS):
❑ Configurable serial data:
❑ USB3.1SSP+ data rates:
■ 5Gbps,
■ 10Gbps
❑ DP Alt data rates:
■ 1.620Gbps
■ 2.700Gbps
■ 5.400Gbps
■ 8.100Gbps
❑ Quad channel macros configurations lanes for multiport Type-C - USB3.1SSP+/DPAlt PHY.
❑ Extensive PMA debug capability through read/write and read-only registers in PCS.
❑ Register-based control of all PCS-to-PMA signals.
❑Adaptive and configurable RX continuous time linear equalizer (CTLE) and decision feedback
equalizer (DFE).
❑ Programmable TX equalization.
■ IEEE 1149.1 and 1149.6 (AC JTAG) boundary scan.
■ Built-in Self-Test (BIST) features for production; at-speed testing on any digital tester.
■ Advanced, built-in diagnostics including on-chip sampling scope.
■ Visibility and controllability of hard macro functions through programmable registers in the design:
❑ Overrides on all ASIC side functional control inputs for easy debug .
❑ Access register space through a parallel interface.
❑ Access register space through a JTAG port.
■ Configurable PCS with extensive debug options:
❑ Independent TX and RX control per lane.
❑ Configurable TX and RX power modes.
❑ Pseudo-random bit sequence (PRBS) generation and checker (PRBS31, PRBS23, PRBS16, PRBS15,
PRBS11, PRBS9, PRBS7).
❑ Programmable 10-bit pattern generation with error injection capability.
■ Built-in, on-chip SSC generation and full configuration from -5000ppm to +5000ppm with a
maximum range of 5000ppm.

■ A reference clock repeater for other modules.
■ Supports flip-chip packaging

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