『三味书屋』元旦送礼之六：著名的Kluwer丛书系列 Volume 675～759

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	Design and Analysis of High Efficiency Line Drivers for xDSL(直接点击论坛附件链接) Series: The Springer International Series in Engineering and Computer Science , Vol. 759 Piessens, Tim, Steyaert, Michiel 2004, 235 p., Hardcover ISBN: 978-1-4020-7727-2 This item usually ships in 3-4 weeks.
	$159.00

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Design and Analysis of High Efficiency Line Drivers for xDSL covers the most important building block of an xDSL (ADSL, VDSL, ...) system: the line driver. Traditional Class AB line drivers consume more than 70% of the total power budget of state-of-the-art ADSL modems. This book describes the main difficulties in designing line drivers for xDSL. The most important specifications are elaborated staring from the main properties of the channel and the signal properties. The traditional (class AB), state-of-the-art (class G) and future technologies (class K) are discussed.
The main part of Design and Analysis of High Efficiency Line Drivers for xDSL describes the design of a novel architecture: the Self-Oscillating Power Amplifier or SOPA. This architecture uses a non-linear, asynchronous modulation scheme that enables highly efficient, highly linear transmission. The concept has been proven by two implementations in a digital CMOS technology: a G-Lite compliant line driver with 61% efficiency and a full ADSL-VDSL downstream compliant power amplifier with 47% power efficiency. The proposed architecture is fully analysed and complete design plans including CMOS scaling laws and software tools to facilitate the design of these types of amplifiers are extensively described.
Since the analysis of a SOPA amplifier involves advanced non-linear system design techniques, Design and Analysis of High Efficiency Line Drivers for xDSL presents extensively advanced non-linear analysis techniques which not only aid the design of high efficiency line drivers but are also applicable in other domains of analog system design.
Therefore Design and Analysis of High Efficiency Line Drivers for xDSL can be read not only as an exhaustive tutorial on the basic properties and limitations of an xDSL line driver, but also as a tutorial on advanced non-linear system design and a design manual of a highly efficient switching power amplifier.
Written for:
Scientists, researchers

[ 本帖最后由 benemale 于 2008-1-5 12:04 编辑 ]

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	High Data Rate Transmitter Circuits   RF CMOS Design and Techniques for Design Automation(直接点击论坛附件链接) Series: The Springer International Series in Engineering and Computer Science , Vol. 747 Ranter, C.J. de, Steyaert, Michiel 2003, 235 p., Hardcover ISBN: 978-1-4020-7545-2 Ships in 3 - 5 business days
	$149.00

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High Data Rate Transmitter Circuits is a practical guide and introduction to the design of key RF building blocks used in high data rate transmitters. The emphasis lies on CMOS circuit techniques applicable to oscillators and upconvertors. Furthermore, a method for RF-specific design automation is exemplified by the CYCLONE tool for automated LC-VCO synthesis.
The accuracy of a simulation depends strongly on the models used for the passive and active components. Therefore, a chapter on practical RF simulation models for MOST devices and planar inductors is included. Polyphase networks can be used for quadrature signal generation and as a complex filter. The book describes in detail the analytical calculations on such networks and includes a practical simulation-based design approach. The final manufacturing step before measuring a chip is the bonding process. In a short chapter the flip-chip bonding technique is discussed and the negative influence of X-ray inspection on chip performance is demonstrated.
High data rate systems need low phase-noise oscillators. The design of a 17GHz VCO as presented in this book demonstrates the possible use of a CMOS technology for fixed-wireless or high-speed optical system integration. Using a polyphase network as a complex filter, a ringoscillator with over a decade of tuning range has been linearized for use in HFC-like cable systems. This technique is discussed elaborately in a chapter on broadband oscillators. As a typical design case of a high data rate building block, the design of a wideband CMOS transmitter circuit is presented. Starting from a market overview, the target specifications are derived. A high-level circuit design is then gradually refined down to transistor level and ultimately layout. In a concluding chapter, the measured performance is discussed.
Written in an easily accessible manner, High Data Rate Transmitter Circuits is essential reading for both students and practicing engineers interested in analog RF design and RF-specific design automation. The book has been praised for its pleasant and light style of writing, without losing detail on the technical side.

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Students and practicing engineers interested in analog RF design and RF-specific design automation

[ 本帖最后由 benemale 于 2008-1-5 12:13 编辑 ]

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	Low-Voltage CMOS Log Companding Analog Design Series: The Springer International Series in Engineering and Computer Science , Vol. 733 Serra-Graells, Francisco, Rueda, Adoración, Huertas, José L. 2003, 220 p., Hardcover ISBN: 978-1-4020-7445-5 Ships in 3 - 5 business days
	$149.00

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Low-Voltage CMOS Log Companding Analog Design presents in detail state-of-the-art analog circuit techniques for the very low-voltage and low-power design of systems-on-chip in CMOS technologies. The proposed strategy is mainly based on two bases: the Instantaneous Log Companding Theory, and the MOSFET operating in the subthreshold region. The former allows inner compression of the voltage dynamic-range for very low-voltage operation, while the latter is compatible with CMOS technologies and suitable for low-power circuits. The required background on the specific modeling of the MOS transistor for Companding is supplied at the beginning. Following this general approach, a complete set of CMOS basic building blocks is proposed and analyzed for a wide variety of analog signal processing. In particular, the covered areas include: amplification and AGC, arbitrary filtering, PTAT generation, and pulse duration modulation (PDM). For each topic, several case studies are considered to illustrate the design methodology. Also, integrated examples in 1.2um and 0.35um CMOS technologies are reported to verify the good agreement between design equations and experimental data. The resulting analog circuit topologies exhibit very low-voltage (i.e. 1V) and low-power (few tenths of uA) capabilities. Apart from these specific design examples, a real industrial application in the field of hearing aids is also presented as the main demonstrator of all the proposed basic building blocks. This system-on-chip exhibits true 1V operation, high flexibility through digital programmability and very low-power consumption (about 300uA including the Class-D amplifier). As a result, the reported ASIC can meet the specifications of a complete family of common hearing aid models. In conclusion, this book is addressed to both industry ASIC designers who can apply its contents to the synthesis of very low-power systems-on-chip in standard CMOS technologies, as well as to the teachers of modern circuit design in electronic engineering.
Written for:
ASIC designers, teachers of modern circuit design in electronic engineering

[ 本帖最后由 benemale 于 2008-1-5 00:08 编辑 ]

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	Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems Series: The Springer International Series in Engineering and Computer Science , Vol. 722 Keh-La Lin, Kemna, Armin, Hosticka, Bedrich J. 2003, 254 p., Hardcover ISBN: 978-1-4020-7380-9 Ships in 3 - 5 business days
	$179.00

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One of the main trends of microelectronics is toward design for integrated systems, i.e., system-on-a-chip (SoC) or system-on-silicon (SoS). Due to this development, design techniques for mixed-signal circuits become more important than before. Among other devices, analog-to-digital and digital-to-analog converters are the two bridges between the analog and the digital worlds. Besides, low-power design technique is one of the main issues for embedded systems, especially for hand-held applications.
Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems aims at design techniques for low-power, high-speed analog-to-digital converter processed by the standard CMOS technology. Additionally this book covers physical integration issues of A/D converter integrated in SoC, i.e., substrate crosstalk and reference voltage network design.

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Researchers, scientists

[ 本帖最后由 benemale 于 2008-1-5 00:19 编辑 ]

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	CMOS Fractional-N Synthesizers  Design for High Spectral Purity and Monolithic Integration (直接点击论坛附件链接) Series: The Springer International Series in Engineering and Computer Science , Vol. 724 De Muer, Bram, Steyaert, Michiel 2003, 270 p., Hardcover ISBN: 978-1-4020-7387-8 Ships in 3 - 5 business days
	$199.00

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CMOS Fractional-N Synthesizers fits in the quest for small and cheap cellular transceiver solutions. The book is conceived as a manual for the design of fully integrated DeltaSigma fractional-N frequency synthesizers in CMOS with a focus on achieving a high spectral purity, i.e. low-phase-noise and high spurious suppression. Fractional-N design is elaborated from specification derivation up to architectural and building block level and down to circuit level.
CMOS Fractional-N Synthesizers starts with a comprehensive introduction to general frequency synthesis. Different architectures and synthesizer building blocks are discussed with their relative importance on synthesizer specifications. The process of synthesizer specification derivation is illustrated with the DCS-1800 standard as a general test case.
The book tackles the design of fractional-N synthesizers in CMOS on circuit level as well as system level. The circuit level focuses on high-speed prescaler design up to 12 GHz in CMOS and on fully integrated, low-phase-noise LC-VCO design. High-Q inductor integration and simulation in CMOS is elaborated and flicker noise minimization techniques are presented, ranging from bias point choice to noise filtering techniques.
On a higher level, a systematic design strategy has been developed that trades off all noise contributions and fast dynamics for integrated capacitance (area). Moreover, a theoretical DeltaSigma phase noise analysis is presented, extended with a fast non-linear analysis method to accurately predict the influence of PLL non-linearities on the spectral purity of the DeltaSigma fractional-N frequency synthesizers.
CMOS Fractional-N Synthesizers covers the total design flow of monolithic CMOS fractional-N synthesizers with high spectral purity while providing insight in the most critical issues of monolithic fractional-N synthesis. All material is experimentally verified with several CMOS implementations, with ultimately a monolithic CMOS &Dgr;&Sgr;-controlled fractional-N synthesizer, which was part of a CMOS DCS-1800 transceiver front-end. The book is essential reading for analog and RF design engineers and researchers in the field and it is also suitable as text book for an advanced course on the subject.

Written for:
Analog and RF design engineers, researchers in the field

[ 本帖最后由 benemale 于 2008-1-5 12:20 编辑 ]

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	Design Criteria for Low Distortion in Feedback Opamp Circuits Series: The Springer International Series in Engineering and Computer Science , Vol. 720 Hernes, Bjørnar, Sæther, Trond 2003, 170 p., Hardcover ISBN: 978-1-4020-7356-4 This item usually ships in 2-3 business days
	$179.00

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Broadband opamps for multi-channel communication systems have strong demands on linearity performance. When these opamps are integrated in deep sub-micron CMOS technologies, the signal-swing has to occupy a large part of the rather low supply voltage to maintain the signal-to-noise-ratio. To obtain opamps with low distortion it is necessary to do a thorough analysis of the nonlinear behaviour of such circuits and this is the main subject of Design Criteria for Low Distortion in Feedback Opamp Circuits.
The biasing of each transistor in the circuit is a major issue and is addressed in this work. It is important to bias the transistor such that the distortion is low and stable in the entire range of its terminal voltages. This will ensure high linearity and robustness against variations in circuit conditions such as power supply voltage, bias current and process variations.
Design Criteria for Low Distortion in Feedback Opamp Circuits is written for .

Written for:
Analog CMOS designers

[ 本帖最后由 benemale 于 2008-1-5 00:24 编辑 ]

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	Circuit Techniques for Low-Voltage and High-Speed A/D Converters Series: The Springer International Series in Engineering and Computer Science , Vol. 709 Waltari, Mikko E., Halonen, Kari A.I. 2002, 265 p., Hardcover ISBN: 978-1-4020-7244-4 Ships in 3 - 5 business days
	$199.00

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.
Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.
It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.
An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.
The throughput of ADCs can be increased by using parallelism. This is demonstrated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed.
Circuit Techniques for Low-Voltage and High-Speed A/D Converters presents a total of seven prototypes: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO techniques. This monograph will prove to be a useful reference for both academics and professionals whom are active in the Analog Circuit Design and Communications field.

[ 本帖最后由 benemale 于 2008-1-5 00:31 编辑 ]

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	CMOS Circuit Design for RF Sensors(直接点击论坛附件链接) Series: The Springer International Series in Engineering and Computer Science , Vol. 695 Gudnason, Gunnar, Bruun, Erik 2002, 184 p., Hardcover ISBN: 978-1-4020-7127-0 Ships in 3 - 5 business days
	$179.00

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CMOS Circuit Design for RF Sensors is about CMOS circuit design for sensor and actuators to be used in wireless RF systems. The main application is implantable transducers for biomedical purposes such as sensing of nerve signals and electrical stimulation of nerves. Special focus is put on the power and data link in a wireless system with transducers which are powered via the RF link. Novel principles and methods are presented for the regulation of power to the sensors and for the distribution of data and power in an implanted transducer system. One of the main problems in such systems is the transmission of power via an RF link. This problem is analyzed in detail and solutions incorporating an RF magnetic link to the transducers are identified. The theoretical results are supported by experiments from CMOS chips including a system chip for functional electrical stimulation (FES). The work shows that a System on Chip (SoC) solution is feasible using CMOS technology for the RF sensors. The only components which cannot be integrated on the chip are the antenna coil and a capacitor for energy storage.
CMOS Circuit Design for RF Sensors will be a useful reference for academics as well as research scientists whom are active in the field of (Analog) Circuit Design and Sensors.
Written for:
Academics and research scientists whom are active in the field of (Analog) Circuit Design and Sensors

[ 本帖最后由 benemale 于 2008-1-5 12:22 编辑 ]

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	Architectures for RF Frequency Synthesizers(直接点击论坛附件链接) Series: The Springer International Series in Engineering and Computer Science , Vol. 693 Vaucher, Cicero S. 2002, 276 p., Hardcover ISBN: 978-1-4020-7120-1 This item usually ships in 3-4 weeks.
	$209.00

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Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.
Written for:
Electrical and electronic engineers

[ 本帖最后由 benemale 于 2008-1-5 12:30 编辑 ]

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	Design of Multi-Bit Delta-Sigma A/D Converters(直接点击论坛附件链接) Series: The Springer International Series in Engineering and Computer Science , Vol. 686 Geerts, Yves, Steyaert, Michiel, Sansen, Willy 2002, 240 p., Hardcover ISBN: 978-1-4020-7078-5 This item usually ships in 2-3 business days
	$179.00

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Design of Multi-Bit Delta-Sigma A/D Converters discusses both architecture and circuit design aspects of Delta-Sigma A/D converters, with a special focus on multi-bit implementations. The emphasis is on high-speed high-resolution converters in CMOS for ADSL applications, although the material can also be applied for other specification goals and technologies.
Design of Multi-Bit Delta-Sigma A/D Converters starts with a general introduction of the concepts of Delta-Sigma converters. A wide variety of architectures are discussed, ranging from single-loop to cascaded and various multi-bit topologies. These topologies are optimized to obtain stable converters with a high accuracy. A clear overview is provided of the maximum achievable performance of each topology, which allows a designer to select the optimal architecture for a certain specification. Special attention is paid to multi-bit architectures and possible solutions for the linearity problem of the DA converter in the feedback loop of converters.
Several circuit design aspects of multi-bit Delta-Sigma converters are discussed. Various models are provided for a wide range of linear and non-linear circuit imperfections, which can degrade the performance of the converter. These models allow the designer to determine the required specifications for the different building blocks and form the basis of a systematic design procedure. The presented material is combined in a concluding chapter, which illustrates the systematic design procedure for two high-performance converters.
Design of Multi-Bit Delta-Sigma A/D Converters provides a clear comparison of architectures and yields insight into the influence of the most important circuit non-idealities. It will allow you to design robust and high-performance Delta-Sigma AD converters in a shorter time. It is essential reading for analog design engineers and researchers in the field of AD converters and it is also suitable as a text for an advanced course on the subject.

[ 本帖最后由 benemale 于 2008-1-5 12:18 编辑 ]