【下载】SystemVerilog专辑

mscyc0909

"HARDWARE VERIFICATION WITH C++" -- A Practitioner’s Handbook
Part I: C++ and Verification (The Why and How)
Part II: An Open-Source Environment with C++
Part III: Using OOP for Verification (Best Practices)
Part IV: Examples (Putting It All Together)

mscyc0909

"Writing Testbenches using SystemVerilog"
==========================================
CHAPTER 1 What is Verification?
CHAPTER 2 Verification Technologies
CHAPTER 3 The Verification Plan
CHAPTER 4 High-Level Modeling
CHAPTER 5 Stimulus and Response
CHAPTER 6 Architecting Testbenches
CHAPTER 7 Simulation Management
APPENDIX A Coding Guidelines
APPENDIX B Glossary

mscyc0909

"Verification Methodology Manual for SystemVerilog"
=======================================
CHAPTER 1 Introduction
CHAPTER 2 Verification Planning
CHAPTER 3 Assertions
CHAPTER 4 Testbench Infrastructure
CHAPTER 5 Stimulus And Response
CHAPTER 6 Coverage-Driven Verification
CHAPTER 7 Assertions for Formal Tools
CHAPTER 8 System-Level Verification
CHAPTER 9 Processor Integration Verification
APPENDIX A VMM Standard Library Specification
APPENDIX B VMM Checker Library
APPENDIX C XVC Standard Library Specification
APPENDIX D Software Test Framework

mscyc0909

"SystemVerilog for design"
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Chapter 1: Introduction to SystemVerilog
Chapter 2: SystemVerilog Declaration Spaces
Chapter 3: SystemVerilog Literal Values and Built-in Data Types
Chapter 4: SystemVerilog User-Defined and Enumerated Types
Chapter 5: SystemVerilog Arrays, Structures and Unions
Chapter 6: SystemVerilog Procedural Blocks, Tasks and Functions
Chapter 7: SystemVerilog Procedural Statements
Chapter 8: Modeling Finite State Machines with SystemVerilog
Chapter 9: SystemVerilog Design Hierarchy
Chapter 10: SystemVerilog Interfaces
Chapter 11: A Complete Design Modeled with SystemVerilog
Chapter 12: Behavioral and Transaction Level Modeling
Appendix A: The SystemVerilog Formal Definition (BNF)
Appendix B: Verilog and SystemVerilog Reserved Keywords
Appendix C: A History of SUPERLOG, the Beginning of SystemVerilog

mscyc0909

How can I find this book "The Verification Cookbook - AVM"?

mscyc0909

ASSERTION-BASED DESIGN-SECOND EDITION
===================================
Chapter 1 Introduction
Chapter 2 Assertion Methodology
Chapter 3 Specifying RTL Properties
Chapter 4 PLI-Based Assertions
Chapter 5 Functional Coverage
Chapter 6 Assertion Patterns
Chapter 7 Assertion Cookbook
Chapter 8 Specifying Correct Behavior
Appendix A Open Verification Library
Appendix B PSL Property Specification Language
Appendix C SystemVerilog Assertions

mscyc0909

The book, "SystemVerilog Assertion Handbook", is not a clear version, but copy one.
Reminding of mentioned above.

mscyc0909

SYSTEM VERIFICATION
- Proving the Design Solution Satisfies the Requirements
===================================================
1 SETTING THE STAGE
2 ITEM QUALIFICATION VERIFICATION
3 ITEM ACCEPTANCE VERIFICATION
4 SYSTEM TEST AND EVALUATION
5 PROCESS VALIDATION AND VERIFICATION
6 POSTSCRIPT

sheep_07

太强大了~~~

sheep_07

继续~~~~~~~~