【下载】SystemVerilog专辑

yong1362121

谢谢

yong1362121

谢谢

yong1362121

谢谢

yong1362121

谢谢

yong1362121

谢谢

perry0207

Thanks!

perry0207

Thanks!

mscyc0909

It's a draft version of "Digital System Design with Systemverilog".

mscyc0909

SystemVerilog for Verification -- A Guide to Learning the Testbench Language Features
Second Edition
Content:
1. VERIFICATION GUIDELINES
2. DATA TYPES
3. PROCEDURAL STATEMENTS AND ROUTINES
4. CONNECTING THE TESTBENCH AND DESIGN
5. BASIC OOP
6. RANDOMIZATION
7. THREADS AND INTERPROCESS COMMUNICATION
8. ADVANCED OOP AND TESTBENCH GUIDELINES
9. FUNCTIONAL COVERAGE
10. ADVANCED INTERFACES
11. A COMPLETE SYSTEMVERILOG
12. INTERFACING WITH C

mscyc0909

It's worth reading !!
"Hardware Verification with SystemVerilog -- An Object-Oriented Framework"
Chap t e r 1 : I n t r o d u c t i o n
Chap t e r 2 : Wh y S y s t emVe r i l o g ?
Chap t e r 3 : OOP a n d S y s t emVe r i l o g
Chap t e r 4 : A L a y e r e d Ap p r o a c h
Chap t e r 5 : T e a l B a s i c s
Chap t e r 6 : Truss: A Standard V e r i f i c a t i o n F r amewo r k
Chap t e r 7 : T r u s s F l ow
Chap t e r 8 : T r u s s E x amp l e
Chap t e r 9 : T h i n k i n g OOP
Chapter 11: OOP C l a s s e s
Chapter 12: OOP C o n n e c t i o n s
Chapter 13: C o d i n g OOP
Chapter 14: Block- L e v e l Testing
Chapter 15: C h i p - L e v e l T e s t i n g
Chapter 16: T h i n g s t o R ememb e r