vivado原型验证环境问题总结

IC.Michael

【1】irun编译，增加如下设置；搭建irun编译与起verdi小环境；

1. +incdir+$XILINX_VIVADO/data/verilog/src/retarget
   
2. +incdir+$XILINX_VIVADO/data/verilog/src/unimacro
   
3. +incdir+$XILINX_VIVADO/data/verilog/src/unisims
   
4. +incdir+$XILINX_VIVADO/data/verilog/src/xeclib
   
5. +incdir+$XILINX_VIVADO/data/ip/xpm
   
6. +incdir+$XILINX_VIVADO/data/secureip
   
7. 
   
8. -y $XILINX_VIVADO/data/verilog/src/unimacro
   
9. -y $XILINX_VIVADO/data/verilog/src/unisims
   
10. -y $XILINX_VIVADO/data/verilog/src/xeclib
    
11. -y $XILINX_VIVADO/data/ip/xpm
    
12. -y $XILINX_VIVADO/data/secureip
    

复制代码

//$XILINX_VIVADO/data/ip/xpm/xpm_VCOMP.vhd
//$XILINX_VIVADO/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv
$XILINX_VIVADO/data/verilog/src/unisim_retarget_comp.v

//-f $XILINX_VIVADO/data/secureip/secureip_cell.list.f



【2】编译-top选项除指定项目顶层外，还需指定glbl；详见该链接；

DESCRIPTION
For a Verilog design, when I specify the "-top" option for theirun command, the following error displays:
"file: top.v
module worklib.top:v
errors: 0, warnings: 0
file: glbl.v
module worklib.glbl:v
errors: 0, warnings: 0
Elaborating the design hierarchy:
Top level design units:
top
tri0 GSR = glbl.GSR;
ncelab: *E,CUVHNF (./top.v,37|22): Hierarchical name component lookup failed at 'glbl'.
irun: *E,ELBERR: Error during elaboration (status 1), exiting."
The command is "irun top.v glbl.v -top top". How can I resolve it?
SOLUTION
For Verilog, irun can automatically detect top-level units in the design. Using -top disables the automatic calculation of top-level Verilog units, and these units will also have to be specified using -top.
In order to resolve the error, you can either apply the"-top" option for module "glbl" or remove the "-top" option,that is, use following commands instead:
"irun top.v glbl.v -top top -top glbl" or
"irun top.v glbl.v".

【3】添加secureip_cell.list.f编译会报错，暂未解决（已省略路径信息）；

ncvlog: *F,DECERR (/opt/eda/*/*/vivado2021/Vivado/2021.2/data/secureip/gthe2_channel_fast/gthe2_channel_fast_001.vp,593|26): Error while decrypting : unable to load key invalid/blank keyOwner/KeyName (file ),may be wrong key is used for encryption/decryption ).

【4】synplify综合，建议+incdir+及lib信息添加完善，注意文件添加顺序，子模块在上，top模块在下；

IC.Michael

有个点注意下：
（1）【1】中添加的vivado相关是irun编译用的；仿真或synplify综合的时候不需要添加；
（2）$XILINX_VIVADO/data/verilog/src/unisim_retarget_comp.v，这个文件是空壳，在用IES仿真的时候，端口是X；这个文件只是给irun编译pass用的；
（3）仿真的时候需要添加其他库，即用vivado针对特定器件即仿真工具编译出来的lib，具体可参考ug900；