reset 信號, create_clock 優缺點

thjan65

請問版上高手,
reset signal 以create_clock 來定義有甚麼優缺點?

asic_service

如果不想DC给reset fix DRC，插buffer，用set_ideal_net即可。
reset也是需要分析timing，如果是IO上来，应该给set_input_delay，相对于某个clk。

thjan65

根據 user guide.
Clocks you create by using the create_clock command ignore delay effects of the
clock network. Therefore, for accurate timing analysis, you describe the clock network
in terms of its latency and skew. See also clock latency and clock skew.

所以reset signal 以create_clock 定義之後, 沒有任何delay.  必須使用 set_clock_latency.
如果使用set_input_delay指令, 則  不要用create_clock 定義reset signal, 是不是比較正確?

thjan65

根據 DC student guide.
Load balancing is also known as “design rule optimization”, which entails meeting
maximum/minimum transition, capacitance and/or fanout “design rules”. These design rules are
defined in the technology library and apply to non-clock nets. Clock nets are exempt from meeting
these design rules.

在Constraining Designs for Synthesis and Timing Analysis  這本書裏, 作者提到

...... To prevent this, user can define design objects like cells, pins, or nets as ideal, which
implies that such objects are not required to adhere to design rules like maximum
capacitance, fanout, and transition.

所以, 將reset singal 以create_clock 定義. 我覺得效果跟set_ideal_network 似乎一樣. 只是寫法不同.

ricvadim

非常感谢你提供的信息。期待新品的到来