A New Book in Digital Logic Design

carl11223344 · 发表于 2021-12-11 15:07:15

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Here comes the 2nd edition of "Digital Logic Design Using Verilog-Coding and RTL Synthesis", authorized by Vaibbhav Taraate and published by Springer, 2022 series.
Introduction to author:
Vaibbhav Taraate is an entrepreneur and mentor at “1 Rupee S T”. He holds B.E.
(Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold
Medal for standing first in all engineering branches. He completed his M.Tech.
(Aerospace Control and Guidance) at the Indian Institute of Technology
(IIT) Bombay, India, in 1999. He has over 18 years of experience in semi-custom
ASIC and FPGA design, primarily using HDL languages such as Verilog, VHDL
and SystemVerilog. He has worked with multinational corporations as a consultant,
senior design engineer, and technical manager. His areas of expertise include RTL
design using VHDL, RTL design using Verilog, complex FPGA-based design, low
power design, synthesis and optimization, static timing analysis, system design
using microprocessors, high-speed VLSI designs, and architecture design of complex
SOCs.