西安/大厂在西安组建团队 招聘soc/IP各方向设计

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以下是某手机大厂  在西安组建团队 （以下职位需要硕士4年以上，更多职位，欢迎问询）

SOC-SOCdigital design engineer

工作职责
Frontend designer for ASIC projects
Architecture design and RTL implementation of SoCIP designs
Top integration as well as IP evaluation andselection
SoC system performance analysis
工作要求
Master's Degree preferred
Good communication skill
At least 3 years ASIC/SOC design and tape out flowexperience
Experienced in SOC design and IP integration
Experienced in hierarchical design, budgeting,multiple voltage domains and multiple clock domains
Understanding of STA and timing constraints
Preferred/Plus
Experienced in SoC architecture, EmbeddedProcessor(DSP/MCU), and bus (ARM bus) system architecture design
Experience with DDR Design
Experienced in high speed design (>1GHz)
Experienced in working on advanced process nodes(16nm)

SOC-SOCLowpower engineer

工作职责
1. 负责世界顶级芯片的研发和设计工作
2. 和相关部门紧密合作，完成从产品定义、架构定义、逻辑设计、物理设计、验证、流片和量产的全流程
3. 完成IP模块、子系统和SOC层的设计、集成
工作要求
1. 熟悉Synopsys或者Cadence 或者其它EDA工具, 如Spyglass, Linting, CDC，DC (Design Compilier), PT (PrimeTime)
2. 熟悉SoC芯片流程设计 (IC design flow)
3. 熟悉Verilog/SystemVerilog
4. 熟悉低功耗设计, UPF实现流程, 和功耗分析 (power analysis, power optimization, powermanagement, PTPX)

SoC DSPDesign Engineer

工作职责
As DSP IP owner, responsible for delivering RTLand design documents, and supporting soc integration
To evaluate and select DSP core, including itsPPA,SW toolchain and ecosystem, etc
DSP instruction customization, ISA extension andMicro-architecture design to achieve high performance and energy efficiency formobile application
DSP core modeling and PPA simulation/analysis
Coordinate the team efforts on hardware andsoftware co-design for mobile application
工作要求
PhD or Master in Electrical/Computer Engineering,Computer Science, or related fields with working knowledge of:
DSP microarchitecture and instruction set design,Microarchitecture modeling and optimization
Experience of CEVA/Cadence DSP ISA,micro-architecture and pipeline design for high energy efficiency mobileapplication, familiar with DSP arch and instruction set
Familiar with soc design flow, EDA languages suchas Verilog, scripting languages such as Python,VCS/Verdi/Spyglass/DC/Genus/PTPX tools, etc.
Experience of CEVA/Cadence DSP soc integration andverification
Familiar with Cadence TIE, SNPS ASIP is preferred
Experience of audio/vision algorithms orapplications is preferred

System IPDesign Engineer

工作职责
1.负责世界顶级芯片的研发和设计工作
2.和相关部门紧密合作，完成从产品定义，架构定义，逻辑设计，物理设计，验证，流片和量产的全流程
3.完成IP模块， 子系统和SOC层的设计，集成。
工作要求
1. 熟悉Synopsys或者Cadence 或者其它EDA工具, 如Spyglass, Linting, CDC，DC (Design Compilier), PT (PrimeTime),
2. 熟悉SoC芯片流程设计 (IC design flow)
3.熟悉Verilog/SystemVerilog；
4. 熟悉模块级结构设计（IC design, microarchitecture），RTL实现和相关验证工作 (simulation, verification, emulation)
5.熟悉ARM架构和ARM IPs, AXI, AHB, Cache, SMMU, Coresight等
6. 熟悉SoC集成，总线架构设计BUS/NOC，优先
7. 熟悉高速接口设计， 包括： DDR， PCIE， USB， CSI， DSI， Serdes， C-PHY, D-PHY优先
8. 熟悉安全芯片模块, 加解密（crypto engine）优先
9. 熟悉视频图像处理ISP

SOC designEngineer(GPU)
工作职责
1. GPU subsystem integration, RTL coding anddesign spec delivery.
2. Follow up with mainstream GPU arch developmenttrend, dive deep into GPU micro arch, analyze GPU performance and powerefficiency optimization methods.
3. Build GPU system modeling platform andcooperate with software team to analyze user requirement, performance, andpower efficiency.
4. Support IMPL/Backend team to finish GPU areaand power optimization and iteration.
5. GPU subsystem RTL Coding, delivery of SDC, UPFdefinition, and complete Lint/CDC check to deliver a high-quality subsystemdesign.
6. Provide verification requirement on GPU, reviewDV/CV/ test plans, and support CPU DV/CV engineers to finish verification.
工作要求
1. Master’s degree or above inElectronics/Computer or related field, with more than 3 years relevant workingexperience.
2. Experience in SOC design flow and low powerdesign methodology, proficient in using EDA tools such asVCS/Verdi/Spyglass/PTPX as well as script language like Perl/Python.
3. Knowledge on mainstream GPU micro arch such asARM, IMG, Nvidia, AMD, etc and experience on performance/power/areaoptimization is a plus.
4. Knowledge on GPU system level performancemodeling and experience on GPU DVFS, low power design is a plus.
5. Experience on GPU subsystem integration on massproduction chips. Familiar with GPU application scenarios, software/hardwareco-design.
6. Strong sense of responsibility, ability to workunder pressure, good communication and coordination skills are required.

SOC-SoCCPU Design Engineer

工作职责
As MCU IP owner, responsible for delivering RTLand design documents, and supporting soc integration
To evaluate and select MCU core, including itsPPA,SW toolchain and ecosystem
MCU instruction customization, ISA extension andMicro-architecture design to achieve high performance and energy efficiency formobile application
MCU core modeling and PPA simulation/analysis
Coordinate the team efforts on hardware andsoftware co-design for mobile application
工作要求
PhD or Master in Electrical/Computer Engineering,Computer Science, or related fields with working knowledge of:
CPU microarchitecture and instruction set design,Microarchitecture modeling and optimization
Experience of ARM/RISC-V core ISA,micro-architecture and pipeline design for high energy efficiency mobileapplication, familiar with ARM/RISCV arch and instruction set
Familiar with soc design flow, EDA languages suchas Verilog, scripting languages such as Python,VCS/Verdi/Spyglass/DC/Genus/PTPX tools, etc.
Experience of CPU soc integration, familiar withdebug and security system is preferred
Familiar with AMBA/AXI/AHB/APB is preferred

SOC-SystemIP Design Engineer（安全）

职责描述：
负责手机芯片系统安全模块以及安全芯片设计
任职要求：
1. 电子工程、计算机、微电子相关专业，硕士及以上
2. 有信息安全、密码学等专业背景优先
3. 至少3年以上芯片开发、验证、修改、测试经验
4. 熟练掌握Verilog、SystemVerilog等RTL编程语言及微架构设计
5. 熟悉芯片开发、仿真、验证工具和流程
6. 有实现过安全算法（对称、非对称）及国密算法芯片的优先
7. 对安全算法、芯片的攻击方法和相应防护措施有了解，有防攻击电路设计经验优先
8. 对安全芯片传感器设计或集成、验证、测试有了解，有设计或集成经验优先
9. 有安全电路、TrustZone SoC、DMA、Cache、MMU、NVM、KMS、TZPC、Bus Filter控制器的设计或集成经验优先
10. 有TRNG设计或集成、验证经验优先
11. 熟练掌握C/汇编及至少一种脚本语言
12. 有较强的自我驱动和快速学习能力
13. 有良好的文字和语言沟通能力

SOC-ASICEngineer (FPGA Prototyping)

工作职责
ASIC to FPGA modification and integration
Writing testcase to verify FPGA SOC prototyping
FPGA/EMU synthesis, partitioning and emulatingusing Synopsys, Xilinx tools
FPGA prototyping system debug and bringup
Script work for task automation
工作要求
Bachelor degree or above in EE, CS or Automation
3 - 5 years of the professional experience
Good knowledge with FPGA experience includingimplementation, synthesis (Synplify), timing closure (Vivado/ISE)
Familiar with typical FPGA improvement platformssuch as Xilinx, HAPS，Palladium etc
Familiar with HDL language, such like verilog /system Verilog
Strong problem orientation ability
Self-motivated, good communication skill and teamwork player

SoC VIEngineer(power/performance)

作职责
Responsible for the basic software development ofthe chip FPGA/Emulator platform.
Functional validation, performance/powerevaluation/analysis/optimization and support chip MP software delivery forCPU/GPU/DSP/SOC etc. based on bare metal/OS
Responsible for chip user scenarioperformance/power modeling and sign off at pre-silicon, correlation atpost-silicon
工作要求
Master or Bachelor degree in computer,communication engineering, electronics or microelectronics and other relatedmajors.
Familiar with ARM/X86//DSP architecture andembedded operating system, familiar with software development of consumerembedded electronic products.
Experience in verification platforms such asFPGA/PalladiumXP/Zebu is preferred
Familiar with performance/power evaluation testmethods for CPU/GPU/DSP etc. ,familiar with chip development process ispreferred.
Familiar with scripting languages such asPython/TCL and related tool development experience is preferred.
Familiar with CPU/GPU/DSP etc. related driverdevelopment, chip testing, platform software development background ispreferred.
Be responsible, honest and trustworthy, have asense of teamwork spirit, and have a strong ability to withstand pressure.

SOC-SoC VI Engineer(binning)

Work withdesign/DFT/engineering team to develop characterization plan, drive forefficient & effective execution
FT test program development, test patternbring-up/debug for test time reduction and yield improvement
Work out chip binning strategy with big datacollection and analysis
工作要求
Master or Bachelor degree in computer,communication engineering, electronics or microelectronics and other relatedmajors
Experience in ATE test methodology andyield/binning process
Solid programing skills in C/C++ and one of script(Perl, Shell, python etc.)
Familiar with data management systems andstatistical analysis tools
Be responsible, honest and trustworthy, have asense of teamwork spirit, and have a strong ability to withstand pressure.