2021 VLSI wireline paper and slides

mustafa16 · 发表于 2021-6-19 06:02:19

thanks

lwxyear · 发表于 2021-6-20 10:54:37

谢谢分享！！！

mm369932tw · 发表于 2021-6-21 11:03:25

谢谢分享！！！

mm369932tw · 发表于 2021-6-22 15:10:47

请问能否分享
C7-5 A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM
JFS1-3 A 7nm 0.46pJ/bit 20Gbps with BER 1E-25 Die-to-Die Link Using Minimum Intrinsic Auto Alignment and Noise-Immunity
Encode
这两篇也是wireline相关的论文呢
感谢您

cross武 · 发表于 2021-6-25 11:59:40

谢谢分享

peterlin2010 · 发表于 2021-6-25 13:06:06

serdes ?? design

thank you

qmax · 发表于 2021-6-25 13:38:38

tks a lot.

icboy · 发表于 2021-6-26 16:36:47

请问弄否帮忙分享下 SESSION 18
High-Performance Clock Generators ，非常感谢

xjdmgbb · 发表于 2021-6-28 11:48:10

XIEXIE LOUZHU

kldeng1344 · 发表于 2021-6-29 16:42:33

谢谢分享！！！

[原创] 2021 VLSI wireline paper and slides

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