NTU LDO & voltage reference(published in JSSC.2016) design PHD thesis

Rsir!

Chapter 1 Introduction ................................................................................................ 1
1.1 Motivation ................................................................................................. 1
1.2 Objectives ................................................................................................ 11
1.3 Contributions ........................................................................................... 13
1.4 Organization ............................................................................................ 16
Chapter 2 Literature Review .................................................................................... 18
2.1 Review of the design of the LDO ............................................................ 18
2.1.1 Review of the design parameters of an LDO ................................... 18
2.1.2 Review of the LDO topologies ......................................................... 23
2.1.3 Review of the PSRR mechanisms of the LDO ................................ 27
2.1.4 Review of prior-art PSRR enhancing techniques ............................ 33
2.2 Review of the design of the voltage reference ........................................ 37
2.2.1 Review of design parameters of the voltage reference ..................... 37
2.2.2 Review of the design of bandgap references .................................... 39
2.2.3 Review of the subthreshold voltage reference .................................. 52
2.3 Review of radiation effects on ICs .......................................................... 57
2.3.1 Total Ionizing Dose (TID) Effect ..................................................... 57
2.3.2 Single Event Effects (SEEs) ............................................................. 62
2.4 Conclusions ............................................................................................. 64
Chapter 3 A 65nm NMOS LDO for IoTs featuring >60dB PSRR over 10MHz
frequency range and 100mA load current range .................................. 65
3.1. Design of the proposed LDO ................................................................... 66
3.1.1. Design considerations for a high PSRR ........................................... 68
3.1.2. Design considerations for stability ................................................... 83
3.1.3. Design considerations for a low dropout voltage ............................. 89
3.2. Hardware measurements of the proposed LDO ...................................... 91
3.2.1. Static performance measurements .................................................... 91
3.2.2. Load transient measurements ........................................................... 93
3.2.3 PSRR measurements ........................................................................ 96
3.2.4. Noise measurements ....................................................................... 100
3.3. Design summary and Benchmarking ..................................................... 101
3.4. Conclusions ........................................................................................... 103
Chapter 4 A 5.6ppm/°C Temperature Coefficient, 87dB PSRR, sub-1V, rad-hard
MOSFET-only voltage reference exploiting the ZTC point of an
NMOS ...................................................................................................... 104
4.1 Investigation of the ZTC point mechanism ........................................... 105
4.2 Realization and design considerations of the proposed ZTC voltage
reference ....................................................................................................... 110
4.2.1 ZTC voltage reference design ........................................................ 110
4.2.2 PSRR and output noise ................................................................... 112
4.2.3 Process variations ........................................................................... 117
4.3. Hardware measurements of the proposed voltage reference ................. 122
4.4. Design summary and Benchmarking ..................................................... 128
4.5 Irradiation verification of the proposed voltage reference .................... 131
4.6 Conclusions ........................................................................................... 136
Chapter 5 Conclusions and Recommendations ..................................................... 138
5.1 Conclusions ........................................................................................... 138

5.2 Recommendations for future work ........................................................ 140

dcircuit

kankan

rfjungle

thanks!!!

畅游

thanks!!!

amigo.change

寒枫

学习，thanks！

jeffej

very good thesis for ldo design

Robin_LBJ

thx for sharing

mylove2

谢谢楼主的分享！

cdting

Thanks!!!